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authorBin Meng <bmeng.cn@gmail.com>2015-07-06 16:31:31 +0800
committerSimon Glass <sjg@chromium.org>2015-07-14 18:03:18 -0600
commit92587b364b1750612739438810f17c5b98f406fb (patch)
tree7b66e8bb22df08f8cee9bdf96f71f013727c18d7 /arch/x86/cpu/queensbay
parent43dd22f5fc4c368616721a69e5ea0769abf292dc (diff)
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x86: queensbay: Change CPU_ADDR_BITS to 32
Per CPUID:80000008h result, the maximum physical address bits of TunnelCreek processor is 32 instead of default 36. This will fix the incorrect decoding of MTRR range mask. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/queensbay')
-rw-r--r--arch/x86/cpu/queensbay/Kconfig4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 397e599..fbf85f2 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -38,4 +38,8 @@ config CMC_ADDR
The default base address of 0xfffb0000 indicates that the binary must
be located at offset 0xb0000 from the beginning of a 1MB flash device.
+config CPU_ADDR_BITS
+ int
+ default 32
+
endif