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authorSimon Glass <sjg@chromium.org>2014-11-14 18:18:40 -0700
committerSimon Glass <sjg@chromium.org>2014-11-25 06:34:01 -0700
commit9baeca4b8936edc01e1c748a6f119915acb100c4 (patch)
treecc2c484f443f937b560b888186d6c93877bb3d9d /arch/x86/cpu/ivybridge
parent4896f4acc8b67155026cd1095b5dcdb22e70445a (diff)
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x86: ivybridge: Set up EHCI USB
Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/ivybridge')
-rw-r--r--arch/x86/cpu/ivybridge/Makefile1
-rw-r--r--arch/x86/cpu/ivybridge/bd82x6x.c2
-rw-r--r--arch/x86/cpu/ivybridge/usb_ehci.c29
3 files changed, 32 insertions, 0 deletions
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index c6342cd..4a00757 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -17,3 +17,4 @@ obj-y += pci.o
obj-y += report_platform.o
obj-y += sata.o
obj-y += sdram.o
+obj-y += usb_ehci.o
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index b54f5c7..1fcbc28 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -102,6 +102,8 @@ int bd82x6x_init_pci_devices(void)
return -EINVAL;
}
bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
+ bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
+ bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
return 0;
}
diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c
new file mode 100644
index 0000000..291c971
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/usb_ehci.c
@@ -0,0 +1,29 @@
+/*
+ * From Coreboot
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+void bd82x6x_usb_ehci_init(pci_dev_t dev)
+{
+ u32 reg32;
+
+ /* Disable Wake on Disconnect in RMH */
+ reg32 = readl(RCB_REG(0x35b0));
+ reg32 |= 0x22;
+ writel(reg32, RCB_REG(0x35b0));
+
+ debug("EHCI: Setting up controller.. ");
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER;
+ /* reg32 |= PCI_COMMAND_SERR; */
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ debug("done.\n");
+}