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authorSimon Glass <sjg@chromium.org>2016-01-17 16:11:31 -0700
committerBin Meng <bmeng.cn@gmail.com>2016-01-24 12:08:17 +0800
commit9ed781a6ffba48d75b3ae0a0058ca439b8e178c2 (patch)
tree1700cfafb872f8b307f1c547d59576b48e578d29 /arch/x86/cpu/ivybridge/northbridge.c
parentac643e0363b4fe32e2742ede8084fc9999bd0bfb (diff)
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x86: ivybridge: Move northbridge and PCH init into drivers
Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/ivybridge/northbridge.c')
-rw-r--r--arch/x86/cpu/ivybridge/northbridge.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index 6b00d31..2eed0af 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -197,15 +197,12 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev)
dm_pci_write_config8(dev, PAM6, 0x33);
}
-static int bd82x6x_northbridge_probe(struct udevice *dev)
+static int bd82x6x_northbridge_early_init(struct udevice *dev)
{
const int chipset_type = SANDYBRIDGE_MOBILE;
u32 capid0_a;
u8 reg8;
- if (gd->flags & GD_FLG_RELOC)
- return 0;
-
/* Device ID Override Enable should be done very early */
dm_pci_read_config32(dev, 0xe4, &capid0_a);
if (capid0_a & (1 << 10)) {
@@ -226,6 +223,17 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)
return 0;
}
+static int bd82x6x_northbridge_probe(struct udevice *dev)
+{
+ if (!(gd->flags & GD_FLG_RELOC))
+ return bd82x6x_northbridge_early_init(dev);
+
+ northbridge_enable(PCH_DEV);
+ northbridge_init(PCH_DEV);
+
+ return 0;
+}
+
static const struct udevice_id bd82x6x_northbridge_ids[] = {
{ .compatible = "intel,bd82x6x-northbridge" },
{ }