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| author | Simon Glass <sjg@chromium.org> | 2014-11-12 22:42:15 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-11-21 07:34:12 +0100 |
| commit | 2b6051541b562b72d2cf784376a84552da18318d (patch) | |
| tree | c21b6ae92539eb63628f15b52044dd164471aed7 /arch/x86/cpu/ivybridge/cpu.c | |
| parent | 6fb3b72e8745073465b4a5875b7750cc43cbd1af (diff) | |
| download | u-boot-imx-2b6051541b562b72d2cf784376a84552da18318d.zip u-boot-imx-2b6051541b562b72d2cf784376a84552da18318d.tar.gz u-boot-imx-2b6051541b562b72d2cf784376a84552da18318d.tar.bz2 | |
x86: ivybridge: Add early LPC init so that serial works
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/ivybridge/cpu.c')
| -rw-r--r-- | arch/x86/cpu/ivybridge/cpu.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index ff6b7b3..5d7640b 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -11,16 +11,21 @@ */ #include <common.h> +#include <errno.h> +#include <fdtdec.h> #include <asm/cpu.h> #include <asm/pci.h> #include <asm/post.h> #include <asm/processor.h> +#include <asm/arch/pch.h> DECLARE_GLOBAL_DATA_PTR; int arch_cpu_init(void) { + const void *blob = gd->fdt_blob; struct pci_controller *hose; + int node; int ret; post_code(POST_CPU_INIT); @@ -34,6 +39,13 @@ int arch_cpu_init(void) if (ret) return ret; + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + if (node < 0) + return -ENOENT; + ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); + if (ret) + return ret; + return 0; } |