summaryrefslogtreecommitdiff
path: root/arch/x86/cpu/coreboot
diff options
context:
space:
mode:
authorSimon Glass <sjg@chromium.org>2013-04-17 16:13:36 +0000
committerSimon Glass <sjg@chromium.org>2013-05-13 13:33:21 -0700
commite761ecdbb83e3151ffea5b531523256c57e62527 (patch)
treecbd44285af8784933d8c09caba2f0f8208d1856b /arch/x86/cpu/coreboot
parent7949703a9582ec60cf841c595acd3bbe86933cd3 (diff)
downloadu-boot-imx-e761ecdbb83e3151ffea5b531523256c57e62527.zip
u-boot-imx-e761ecdbb83e3151ffea5b531523256c57e62527.tar.gz
u-boot-imx-e761ecdbb83e3151ffea5b531523256c57e62527.tar.bz2
x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/coreboot')
-rw-r--r--arch/x86/cpu/coreboot/timestamp.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c
index 2ca7a57..d26718e 100644
--- a/arch/x86/cpu/coreboot/timestamp.c
+++ b/arch/x86/cpu/coreboot/timestamp.c
@@ -39,7 +39,9 @@ static struct timestamp_table *ts_table __attribute__((section(".data")));
void timestamp_init(void)
{
ts_table = lib_sysinfo.tstamp_table;
- timer_set_tsc_base(ts_table->base_time);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+ timer_set_base(ts_table->base_time);
+#endif
timestamp_add_now(TS_U_BOOT_INITTED);
}