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authorTom Rini <trini@ti.com>2014-11-24 12:00:00 -0500
committerTom Rini <trini@ti.com>2014-11-24 12:00:00 -0500
commit746667f1e56bf08d03e66a178df3c4f4f6c806e1 (patch)
treee42c7fd72cb1ef97a5a05a73b06b3cd2fc118147 /arch/x86/cpu/coreboot
parent6c016485a685b5cdac28edb25147311a3e88d51f (diff)
parentfe5b9b447c6eea3873833b1f3ba15c9854aa2ef8 (diff)
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Merge git://git.denx.de/u-boot-x86
Conflicts: arch/x86/cpu/Makefile Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/x86/cpu/coreboot')
-rw-r--r--arch/x86/cpu/coreboot/coreboot.c42
-rw-r--r--arch/x86/cpu/coreboot/ipchecksum.c2
-rw-r--r--arch/x86/cpu/coreboot/pci.c22
-rw-r--r--arch/x86/cpu/coreboot/sdram.c15
-rw-r--r--arch/x86/cpu/coreboot/tables.c6
5 files changed, 28 insertions, 59 deletions
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index e24f13a..2df7288 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -13,25 +13,25 @@
#include <ns16550.h>
#include <asm/msr.h>
#include <asm/cache.h>
+#include <asm/cpu.h>
#include <asm/io.h>
-#include <asm/arch-coreboot/tables.h>
-#include <asm/arch-coreboot/sysinfo.h>
+#include <asm/arch/tables.h>
+#include <asm/arch/sysinfo.h>
#include <asm/arch/timestamp.h>
DECLARE_GLOBAL_DATA_PTR;
-/*
- * Miscellaneous platform dependent initializations
- */
-int cpu_init_f(void)
+int arch_cpu_init(void)
{
int ret = get_coreboot_info(&lib_sysinfo);
- if (ret != 0)
+ if (ret != 0) {
printf("Failed to parse coreboot tables.\n");
+ return ret;
+ }
timestamp_init();
- return ret;
+ return x86_cpu_init_f();
}
int board_early_init_f(void)
@@ -50,27 +50,9 @@ int board_early_init_r(void)
return 0;
}
-void show_boot_progress(int val)
+int print_cpuinfo(void)
{
-#if MIN_PORT80_KCLOCKS_DELAY
- /*
- * Scale the time counter reading to avoid using 64 bit arithmetics.
- * Can't use get_timer() here becuase it could be not yet
- * initialized or even implemented.
- */
- if (!gd->arch.tsc_prev) {
- gd->arch.tsc_base_kclocks = rdtsc() / 1000;
- gd->arch.tsc_prev = 0;
- } else {
- uint32_t now;
-
- do {
- now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
- } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
- gd->arch.tsc_prev = now;
- }
-#endif
- outb(val, 0x80);
+ return default_print_cpuinfo();
}
int last_stage_init(void)
@@ -98,7 +80,7 @@ int board_eth_init(bd_t *bis)
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-int board_final_cleanup(void)
+void board_final_cleanup(void)
{
/* Un-cache the ROM so the kernel has one
* more MTRR available.
@@ -120,8 +102,6 @@ int board_final_cleanup(void)
/* Issue SMI to Coreboot to lock down ME and registers */
printf("Finalizing Coreboot\n");
outb(0xcb, 0xb2);
-
- return 0;
}
void panic_puts(const char *str)
diff --git a/arch/x86/cpu/coreboot/ipchecksum.c b/arch/x86/cpu/coreboot/ipchecksum.c
index 57733d8..5f6c009 100644
--- a/arch/x86/cpu/coreboot/ipchecksum.c
+++ b/arch/x86/cpu/coreboot/ipchecksum.c
@@ -30,7 +30,7 @@
*/
#include <compiler.h>
-#include <asm/arch-coreboot/ipchecksum.h>
+#include <asm/arch/ipchecksum.h>
unsigned short ipchksum(const void *vptr, unsigned long nbytes)
{
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index b35d70c..6a3dd93 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -13,8 +13,6 @@
#include <pci.h>
#include <asm/pci.h>
-static struct pci_controller coreboot_hose;
-
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
{
@@ -31,19 +29,13 @@ static struct pci_config_table pci_coreboot_config_table[] = {
{}
};
-void pci_init_board(void)
+void board_pci_setup_hose(struct pci_controller *hose)
{
- coreboot_hose.config_table = pci_coreboot_config_table;
- coreboot_hose.first_busno = 0;
- coreboot_hose.last_busno = 0;
-
- pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
- PCI_REGION_MEM);
- coreboot_hose.region_count = 1;
-
- pci_setup_type1(&coreboot_hose);
-
- pci_register_hose(&coreboot_hose);
+ hose->config_table = pci_coreboot_config_table;
+ hose->first_busno = 0;
+ hose->last_busno = 0;
- pci_hose_scan(&coreboot_hose);
+ pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
+ PCI_REGION_MEM);
+ hose->region_count = 1;
}
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index 3140b6b..e98a230 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -11,8 +11,10 @@
#include <asm/e820.h>
#include <asm/u-boot-x86.h>
#include <asm/global_data.h>
+#include <asm/init_helpers.h>
#include <asm/processor.h>
#include <asm/sections.h>
+#include <asm/zimage.h>
#include <asm/arch/sysinfo.h>
#include <asm/arch/tables.h>
@@ -79,7 +81,7 @@ ulong board_get_usable_ram_top(ulong total_size)
return (ulong)dest_addr;
}
-int dram_init_f(void)
+int dram_init(void)
{
int i;
phys_size_t ram_size = 0;
@@ -94,10 +96,11 @@ int dram_init_f(void)
gd->ram_size = ram_size;
if (ram_size == 0)
return -1;
- return 0;
+
+ return calculate_relocation_address();
}
-int dram_init_banksize(void)
+void dram_init_banksize(void)
{
int i, j;
@@ -114,10 +117,4 @@ int dram_init_banksize(void)
}
}
}
- return 0;
-}
-
-int dram_init(void)
-{
- return dram_init_banksize();
}
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index 0d91adc..92b7528 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -8,9 +8,9 @@
*/
#include <common.h>
-#include <asm/arch-coreboot/ipchecksum.h>
-#include <asm/arch-coreboot/sysinfo.h>
-#include <asm/arch-coreboot/tables.h>
+#include <asm/arch/ipchecksum.h>
+#include <asm/arch/sysinfo.h>
+#include <asm/arch/tables.h>
/*
* This needs to be in the .data section so that it's copied over during