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authorBin Meng <bmeng.cn@gmail.com>2015-12-10 22:03:04 -0800
committerBin Meng <bmeng.cn@gmail.com>2016-01-13 12:20:14 +0800
commit214feec1c56d0c0f69bdcc677ad75683ed4f7661 (patch)
treeb293b041e76e37d1a2a586465bf2bf13bc15f751 /arch/x86/cpu/baytrail
parent4ce022d396dd293f40b08f05886c21469feb74ea (diff)
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x86: fsp: Set up init runtime buffer in update_fsp_configs()
fsp_init() runtime buffer parameter might be different across different platforms. Move this to update_fsp_configs(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/baytrail')
-rw-r--r--arch/x86/cpu/baytrail/fsp_configs.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
index 9810921..d49b8d2 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -125,13 +125,19 @@ const struct pch_azalia_config azalia_config = {
* If the device tree does not specify an integer setting, use the default
* provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
*/
-void update_fsp_configs(struct fsp_config_data *config)
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
{
struct upd_region *fsp_upd = &config->fsp_upd;
struct memory_down_data *mem;
const void *blob = gd->fdt_blob;
int node;
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
+
fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);