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author | Simon Glass <sjg@chromium.org> | 2015-01-27 22:13:47 -0700 |
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committer | Simon Glass <sjg@chromium.org> | 2015-02-06 12:07:39 -0700 |
commit | 3a1a18ff1867d6f94921a24992354d3a547666d6 (patch) | |
tree | c3501a0edb1d3e92cf863c8f7b31bd32b0586878 /arch/x86/cpu/baytrail/pci.c | |
parent | 00bdd95278e189131f9b5858045c540bf0cce530 (diff) | |
download | u-boot-imx-3a1a18ff1867d6f94921a24992354d3a547666d6.zip u-boot-imx-3a1a18ff1867d6f94921a24992354d3a547666d6.tar.gz u-boot-imx-3a1a18ff1867d6f94921a24992354d3a547666d6.tar.bz2 |
x86: Add support for Intel Minnowboard Max
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.
This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).
Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/baytrail/pci.c')
-rw-r--r-- | arch/x86/cpu/baytrail/pci.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c new file mode 100644 index 0000000..6c291f9 --- /dev/null +++ b/arch/x86/cpu/baytrail/pci.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <pci.h> +#include <asm/pci.h> +#include <asm/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_pci_setup_hose(struct pci_controller *hose) +{ + hose->first_busno = 0; + hose->last_busno = 0; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CONFIG_PCI_MEM_BUS, + CONFIG_PCI_MEM_PHYS, + CONFIG_PCI_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CONFIG_PCI_IO_BUS, + CONFIG_PCI_IO_PHYS, + CONFIG_PCI_IO_SIZE, + PCI_REGION_IO); + + pci_set_region(hose->regions + 2, + CONFIG_PCI_PREF_BUS, + CONFIG_PCI_PREF_PHYS, + CONFIG_PCI_PREF_SIZE, + PCI_REGION_PREFETCH); + + pci_set_region(hose->regions + 3, + 0, + 0, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + hose->region_count = 4; +} |