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authorSimon Glass <sjg@chromium.org>2015-01-01 16:18:07 -0700
committerSimon Glass <sjg@chromium.org>2015-01-13 07:25:00 -0800
commitaff2523f6998dca1f667aa0d26cc8f351c5628dc (patch)
treeae1694272e3fd7124f83e2a5730755943d041dbd /arch/x86/cpu/Makefile
parent3a5659f7cfc0fd99b57fe2ed9e4a9ebde7cf8491 (diff)
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x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/Makefile')
-rw-r--r--arch/x86/cpu/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 5033d2b..62e43c0 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -17,5 +17,6 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-y += lapic.o
+obj-y += mtrr.o
obj-$(CONFIG_PCI) += pci.o
obj-y += turbo.o