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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2012-08-21 13:14:46 +0900
committerNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2012-08-21 15:00:33 +0900
commit73f35e0b156c771333d449ca86b99600d094d37f (patch)
treec6a12e577144fc1d888684730774910147346e7e /arch/sh/include
parente66443fdb5355e68cfdbbdd37248c4b7eb4968f5 (diff)
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sh: tmu: Changed TMU driver using array of structures
This changed into access using array of structure from access to the register using the definition of the register by macro. And removed white space. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/clk.h5
-rw-r--r--arch/sh/include/asm/cpu_sh7706.h5
-rw-r--r--arch/sh/include/asm/cpu_sh7710.h5
-rw-r--r--arch/sh/include/asm/cpu_sh7720.h10
-rw-r--r--arch/sh/include/asm/cpu_sh7722.h11
-rw-r--r--arch/sh/include/asm/cpu_sh7723.h11
-rw-r--r--arch/sh/include/asm/cpu_sh7724.h11
-rw-r--r--arch/sh/include/asm/cpu_sh7734.h4
-rw-r--r--arch/sh/include/asm/cpu_sh7750.h21
-rw-r--r--arch/sh/include/asm/cpu_sh7757.h14
-rw-r--r--arch/sh/include/asm/cpu_sh7763.h5
-rw-r--r--arch/sh/include/asm/cpu_sh7780.h24
-rw-r--r--arch/sh/include/asm/cpu_sh7785.h24
13 files changed, 11 insertions, 139 deletions
diff --git a/arch/sh/include/asm/clk.h b/arch/sh/include/asm/clk.h
index 9cac6b0..2164bfb 100644
--- a/arch/sh/include/asm/clk.h
+++ b/arch/sh/include/asm/clk.h
@@ -27,9 +27,4 @@ static inline unsigned long get_peripheral_clk_rate(void)
return CONFIG_SYS_CLK_FREQ;
}
-static inline unsigned long get_tmu0_clk_rate(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#endif /* __ASM_SH_CLK_H__ */
diff --git a/arch/sh/include/asm/cpu_sh7706.h b/arch/sh/include/asm/cpu_sh7706.h
index d093f88..8066ff7 100644
--- a/arch/sh/include/asm/cpu_sh7706.h
+++ b/arch/sh/include/asm/cpu_sh7706.h
@@ -41,10 +41,7 @@
#define SCIF0_BASE SCSMR_2
/* Timer */
-#define TSTR0 0xFFFFFE92
-#define TSTR TSTR0
-#define TCNT0 0xFFFFFE98
-#define TCR0 0xFFFFFE9C
+#define TMU_BASE 0xFFFFFE90
/* On chip oscillator circuits */
#define WTCNT 0xFFFFFF84
diff --git a/arch/sh/include/asm/cpu_sh7710.h b/arch/sh/include/asm/cpu_sh7710.h
index e223f1c..e4ecef7 100644
--- a/arch/sh/include/asm/cpu_sh7710.h
+++ b/arch/sh/include/asm/cpu_sh7710.h
@@ -51,10 +51,7 @@
#define SCIF1_BASE SCSMR_1
/* Timer */
-#define TSTR0 0xA412FE92
-#define TSTR TSTR0
-#define TCNT0 0xa412FE98
-#define TCR0 0xa412FE9C
+#define TMU_BASE 0xA412FE90
/* On chip oscillator circuits */
#define FRQCR 0xA415FF80
diff --git a/arch/sh/include/asm/cpu_sh7720.h b/arch/sh/include/asm/cpu_sh7720.h
index 1b393b8..a8013cc 100644
--- a/arch/sh/include/asm/cpu_sh7720.h
+++ b/arch/sh/include/asm/cpu_sh7720.h
@@ -105,16 +105,6 @@
/* TMU */
#define TMU_BASE 0xA412FE90
-#define TSTR (TMU_BASE + 0x02)
-#define TCOR0 (TMU_BASE + 0x04)
-#define TCNT0 (TMU_BASE + 0x08)
-#define TCR0 (TMU_BASE + 0x0C)
-#define TCOR1 (TMU_BASE + 0x10)
-#define TCNT1 (TMU_BASE + 0x14)
-#define TCR1 (TMU_BASE + 0x18)
-#define TCOR2 (TMU_BASE + 0x1C)
-#define TCNT2 (TMU_BASE + 0x20)
-#define TCR2 (TMU_BASE + 0x24)
/* TPU */
#define TPU_BASE 0xA4480000
diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h
index 3157dcb..92dfe27 100644
--- a/arch/sh/include/asm/cpu_sh7722.h
+++ b/arch/sh/include/asm/cpu_sh7722.h
@@ -226,16 +226,7 @@
/* TMU */
-#define TSTR 0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR1 0xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR2 0xFFD80028
+#define TMU_BASE 0xFFD80000
/* TPU */
#define TPU_TSTR 0xA4C90000
diff --git a/arch/sh/include/asm/cpu_sh7723.h b/arch/sh/include/asm/cpu_sh7723.h
index 6dac6e9..2595f29 100644
--- a/arch/sh/include/asm/cpu_sh7723.h
+++ b/arch/sh/include/asm/cpu_sh7723.h
@@ -95,16 +95,7 @@
#define WTCNT RWTCNT
/* TMU */
-#define TSTR 0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR1 0xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR2 0xFFD80028
+#define TMU_BASE 0xFFD80000
/* TPU */
diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h
index 3bb51d3..cd40b6d 100644
--- a/arch/sh/include/asm/cpu_sh7724.h
+++ b/arch/sh/include/asm/cpu_sh7724.h
@@ -116,16 +116,7 @@
#define WTCNT RWTCNT
/* TMU */
-#define TSTR 0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR1 0xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR2 0xFFD80028
+#define TMU_BASE 0xFFD80000
/* TPU */
diff --git a/arch/sh/include/asm/cpu_sh7734.h b/arch/sh/include/asm/cpu_sh7734.h
index 0f84b4f..179a357 100644
--- a/arch/sh/include/asm/cpu_sh7734.h
+++ b/arch/sh/include/asm/cpu_sh7734.h
@@ -36,9 +36,7 @@
#define SCIF5_BASE 0xFFE45000
/* Timer */
-#define TSTR 0xFFD80004
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
+#define TMU_BASE 0xFFD80000
/* PFC */
#define PMMR (0xFFFC0000)
diff --git a/arch/sh/include/asm/cpu_sh7750.h b/arch/sh/include/asm/cpu_sh7750.h
index b3e8424..88c4c8d 100644
--- a/arch/sh/include/asm/cpu_sh7750.h
+++ b/arch/sh/include/asm/cpu_sh7750.h
@@ -143,26 +143,7 @@
#define CLKSTPCLR 0xFE0A0008
/* TMU */
-#define TSTR2 0xFE100004
-#define TCOR3 0xFE100008
-#define TCNT3 0xFE10000C
-#define TCR3 0xFE100010
-#define TCOR4 0xFE100014
-#define TCNT4 0xFE100018
-#define TCR4 0xFE10001C
-#define TOCR 0xFFD80000
-#define TSTR0 0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR1 0xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR2 0xFFD80028
-#define TCPR2 0xFFD8002C
-#define TSTR TSTR0
+#define TMU_BASE 0xFFD80000
/* SCI */
#define SCSMR1 0xFFE00000
diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h
index 17a6537..43c1f07 100644
--- a/arch/sh/include/asm/cpu_sh7757.h
+++ b/arch/sh/include/asm/cpu_sh7757.h
@@ -51,19 +51,7 @@ struct mmu_regs {
#define SMR0 0xfe470000
/* TMU0 */
-#define TSTR 0xFE430004
-#define TOCR 0xFE430000
-#define TSTR0 0xFE430004
-#define TCOR0 0xFE430008
-#define TCNT0 0xFE43000C
-#define TCR0 0xFE430010
-#define TCOR1 0xFE430014
-#define TCNT1 0xFE430018
-#define TCR1 0xFE43001C
-#define TCOR2 0xFE430020
-#define TCNT2 0xFE430024
-#define TCR2 0xFE430028
-#define TCPR2 0xFE43002C
+#define TMU_BASE 0xFE430000
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
diff --git a/arch/sh/include/asm/cpu_sh7763.h b/arch/sh/include/asm/cpu_sh7763.h
index 78b456b..36d7065 100644
--- a/arch/sh/include/asm/cpu_sh7763.h
+++ b/arch/sh/include/asm/cpu_sh7763.h
@@ -43,9 +43,6 @@
#define WDTST 0xFFCC0000
/* TMU */
-#define TSTR 0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
+#define TMU_BASE 0xFFD80000
#endif /* _ASM_CPU_SH7763_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7780.h b/arch/sh/include/asm/cpu_sh7780.h
index e9c59fe..162aa68 100644
--- a/arch/sh/include/asm/cpu_sh7780.h
+++ b/arch/sh/include/asm/cpu_sh7780.h
@@ -272,29 +272,7 @@
#define MSTPCR 0xFFC80030
/* Timer Unit */
-#define TSTR TSTR0
-#define TOCR 0xFFD80000
-#define TSTR0 0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR1 0xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR2 0xFFD80028
-#define TCPR2 0xFFD8002C
-#define TSTR1 0xFFDC0004
-#define TCOR3 0xFFDC0008
-#define TCNT3 0xFFDC000C
-#define TCR3 0xFFDC0010
-#define TCOR4 0xFFDC0014
-#define TCNT4 0xFFDC0018
-#define TCR4 0xFFDC001C
-#define TCOR5 0xFFDC0020
-#define TCNT5 0xFFDC0024
-#define TCR5 0xFFDC0028
+#define TMU_BASE 0xFFD80000
/* Timer/Counter */
#define CMTCFG 0xFFE30000
diff --git a/arch/sh/include/asm/cpu_sh7785.h b/arch/sh/include/asm/cpu_sh7785.h
index 4a4dfc9..8e3839d 100644
--- a/arch/sh/include/asm/cpu_sh7785.h
+++ b/arch/sh/include/asm/cpu_sh7785.h
@@ -46,29 +46,7 @@
#define WDTBCNT 0xFFCC0018
/* Timer Unit */
-#define TSTR TSTR0
-#define TOCR 0xFFD80000
-#define TSTR0 0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR1 0xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR2 0xFFD80028
-#define TCPR2 0xFFD8002C
-#define TSTR1 0xFFDC0004
-#define TCOR3 0xFFDC0008
-#define TCNT3 0xFFDC000C
-#define TCR3 0xFFDC0010
-#define TCOR4 0xFFDC0014
-#define TCNT4 0xFFDC0018
-#define TCR4 0xFFDC001C
-#define TCOR5 0xFFDC0020
-#define TCNT5 0xFFDC0024
-#define TCR5 0xFFDC0028
+#define TMU_BASE 0xFFD80000
/* Serial Communication Interface with FIFO */
#define SCIF1_BASE 0xffeb0000
generated by cgit v1.1 at 2024-11-11 03:43:17 +0000