Merge branch 'master' of /home/wd/git/u-boot/master

14 files changed, 62 insertions, 43 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index f15d43c..3f80700 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -74,7 +74,7 @@ int checkcpu (void)
 		puts("Unicore software on multiprocessor system!!\n"
 		     "To enable mutlticore build define CONFIG_MP\n");
 #endif
-		volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+		volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 		printf("CPU%d:  ", pic->whoami);
 	} else {
 		puts("CPU:   ");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2c3be6d..27236a0 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -179,7 +179,7 @@ static void corenet_tb_init(void)
 	volatile ccsr_rcpm_t *rcpm =
 		(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 	volatile ccsr_pic_t *pic =
-		(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+		(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 	u32 whoami = in_be32(&pic->whoami);
 
 	/* Enable the timebase register for this core */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 8e7b827..4540364 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -54,18 +54,19 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 		u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 
 		if (reg) {
+			u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
+			val = cpu_to_fdt32(val);
 			if (*reg == id) {
-				fdt_setprop_string(blob, off, "status", "okay");
+				fdt_setprop_string(blob, off, "status",
+								"okay");
 			} else {
-				u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
-				val = cpu_to_fdt32(val);
 				fdt_setprop_string(blob, off, "status",
 								"disabled");
-				fdt_setprop_string(blob, off, "enable-method",
-								"spin-table");
-				fdt_setprop(blob, off, "cpu-release-addr",
-						&val, sizeof(val));
 			}
+			fdt_setprop_string(blob, off, "enable-method",
+							"spin-table");
+			fdt_setprop(blob, off, "cpu-release-addr",
+					&val, sizeof(val));
 		} else {
 			printf ("cpu NULL\n");
 		}
diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c
index ac8c01a..a62b031 100644
--- a/arch/powerpc/cpu/mpc85xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc85xx/interrupts.c
@@ -35,7 +35,7 @@
 
 int interrupt_init_cpu(unsigned int *decrementer_count)
 {
-	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR;
+	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
 
 	out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
 	while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index e05257c..603baef 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -38,7 +38,7 @@ u32 get_my_id()
 
 int cpu_reset(int nr)
 {
-	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 	out_be32(&pic->pir, 1 << nr);
 	/* the dummy read works around an errata on early 85xx MP PICs */
 	(void)in_be32(&pic->pir);
@@ -207,7 +207,7 @@ static void plat_mp_up(unsigned long bootpg)
 	gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
 	rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
-	pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+	pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 
 	nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
 
@@ -272,7 +272,7 @@ static void plat_mp_up(unsigned long bootpg)
 	volatile u32 bpcr;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 	u32 devdisr;
 	int timeout = 10;
 
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index 3861146..a6cfaa5 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -81,10 +81,10 @@ struct liodn_id_table fman2_liodn_tbl[] = {
 #endif
 
 struct liodn_id_table sec_liodn_tbl[] = {
-	SET_SEC_JQ_LIODN_ENTRY(0, 146, 154),
-	SET_SEC_JQ_LIODN_ENTRY(1, 147, 155),
-	SET_SEC_JQ_LIODN_ENTRY(2, 178, 186),
-	SET_SEC_JQ_LIODN_ENTRY(3, 179, 187),
+	SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
+	SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
+	SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
+	SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
 	SET_SEC_RTIC_LIODN_ENTRY(a, 144),
 	SET_SEC_RTIC_LIODN_ENTRY(b, 145),
 	SET_SEC_RTIC_LIODN_ENTRY(c, 176),
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index 7e96664..7800717 100644
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c
@@ -288,7 +288,7 @@ UnknownException(struct pt_regs *regs)
 void
 ExtIntException(struct pt_regs *regs)
 {
-	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 
 	uint vect;
 
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 97a94f4..5b30fbd 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -110,13 +110,15 @@ struct cpu_type *identify_cpu(u32 ver)
 }
 
 int cpu_numcores() {
-	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR;
+	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
 	struct cpu_type *cpu = gd->cpu;
 
 	/* better to query feature reporting register than just assume 1 */
+#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
+#define MPC8xxx_PICFRR_NCPU_SHIFT 8
 	if (cpu == &cpu_type_unknown)
-		return ((in_be32(&pic->frr) & MPC85xx_PICFRR_NCPU_MASK) >>
-			MPC85xx_PICFRR_NCPU_SHIFT) + 1;
+		return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
+			MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
 
 	return cpu->num_cores;
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index dccb7aa..e82082e 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -613,6 +613,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_FSL_DDR3)
 	md_en = popts->mirrored_dimm;
 #endif
+	rcw_en = popts->registered_dimm_en;
 	qd_en = popts->quad_rank_present ? 1 : 0;
 	ddr->ddr_sdram_cfg_2 = (0
 		| ((frc_sr & 0x1) << 31)
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index c04eede..b31bd0b 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq)
 	 * modify it.
 	 */
 	if (temp == 1) {
-		mfcpr(CPR0_PLLD, reg);
-		/* Get current value of fbdv.  */
-		temp = (reg & PLLD_FBDV_MASK) >> 24;
-		fbdv = temp ? temp : 32;
-		/* Get current value of lfbdv. */
-		temp = (reg & PLLD_LFBDV_MASK);
-		lfbdv = temp ? temp : 64;
 		/*
 		 * Load register that contains current boot strapping option.
 		 */
 		mfcpr(CPR0_ICFG, reg);
-		/* Shift strapping option into low 3 bits.*/
-		reg = (reg >> 28);
+		/*
+		 * Strapping option bits (ICS) are already in correct position,
+		 * only masking needed.
+		 */
+		reg &= CPR0_ICFG_ICS_MASK;
 
 		if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
 		    (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
+			mfcpr(CPR0_PLLD, reg);
+
+			/* Get current value of fbdv.  */
+			temp = (reg & PLLD_FBDV_MASK) >> 24;
+			fbdv = temp ? temp : 32;
+
+			/* Get current value of lfbdv. */
+			temp = (reg & PLLD_LFBDV_MASK);
+			lfbdv = temp ? temp : 64;
+
 			/*
 			 * Get current value of FWDVA. Assign current FWDVA to
 			 * new FWDVB.
@@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq)
 			mfcpr(CPR0_PLLD, reg);
 			target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
 			fwdvb = target_fwdvb ? target_fwdvb : 8;
+
 			/*
 			 * Get current value of FWDVB. Assign current FWDVB to
 			 * new FWDVA.
 			 */
 			target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
 			fwdva = target_fwdva ? target_fwdva : 16;
+
 			/*
 			 * Update CPR0_PLLD with switched FWDVA and FWDVB.
 			 */
@@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq)
 				((fbdv == 32 ? 0 : fbdv) << 24) |
 				(lfbdv == 64 ? 0 : lfbdv);
 			mtcpr(CPR0_PLLD, reg);
+
 			/* Acknowledge that a reset is required. */
 			reset_needed = 1;
 		}
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 5296dad..4bad32f 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -1459,6 +1459,11 @@ relocate_code:
 	mtspr	SPRN_DTV3,r6
 	msync
 	isync
+
+	/* Invalidate data cache, now no longer our stack */
+	dccci	0,0
+	sync
+	isync
 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
 
 	/*
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index acdc99a..4c17fe2 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -115,11 +115,11 @@ extern void fdt_fixup_liodn(void *blob);
 		FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
 		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \
 
-#define SET_SEC_JQ_LIODN_ENTRY(jqNum, liodnA, liodnB) \
-	SET_LIODN_ENTRY_2("fsl,sec4.0-job-queue", liodnA, liodnB,\
-		offsetof(ccsr_sec_t, jqliodnr[jqNum].ls) + \
+#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
+	SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
+		offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jqNum)
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
 
 /* This is a bit evil since we treat rtic param as both a string & hex value */
 #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index c1382c8..3dd2b7f 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -760,8 +760,6 @@ typedef struct ccsr_pic {
 	u32	eoi;		/* End Of IRQ */
 	u8	res9[3916];
 	u32	frr;		/* Feature Reporting */
-#define MPC85xx_PICFRR_NCPU_MASK	0x00001f00
-#define MPC85xx_PICFRR_NCPU_SHIFT	8
 	u8	res10[28];
 	u32	gcr;		/* Global Configuration */
 #define MPC85xx_PICGCR_RST	0x80000000
@@ -2065,7 +2063,7 @@ typedef struct ccsr_sec {
 	struct {
 		u32	ms;	/* Job Ring LIODN Register, MS */
 		u32	ls;	/* Job Ring LIODN Register, LS */
-	} jqliodnr[4];
+	} jrliodnr[4];
 	u8	res2[0x30];
 	struct {
 		u32	ms;	/* RTIC LIODN Register, MS */
@@ -2110,8 +2108,8 @@ typedef struct ccsr_sec {
 #define SEC_CTPR_MS_AXI_LIODN		0x08000000
 #define SEC_CTPR_MS_QI			0x02000000
 #define SEC_RVID_MA			0x0f000000
-#define SEC_CHANUM_MS_JQNUM_MASK	0xf0000000
-#define SEC_CHANUM_MS_JQNUM_SHIFT	28
+#define SEC_CHANUM_MS_JRNUM_MASK	0xf0000000
+#define SEC_CHANUM_MS_JRNUM_SHIFT	28
 #define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
 #define SEC_CHANUM_MS_DECONUM_SHIFT	24
 #endif
@@ -2301,7 +2299,7 @@ typedef struct ccsr_pme {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC85xx_PIC_ADDR \
+#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index 4bebb68..4e60cbb 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -1250,12 +1250,15 @@ typedef struct immap {
 
 extern immap_t  *immr;
 
-#define CONFIG_SYS_MPC86xx_DDR_OFFSET	(0x2000)
+#define CONFIG_SYS_MPC86xx_DDR_OFFSET	0x2000
 #define CONFIG_SYS_MPC86xx_DDR_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
-#define CONFIG_SYS_MPC86xx_DDR2_OFFSET	(0x6000)
+#define CONFIG_SYS_MPC86xx_DDR2_OFFSET	0x6000
 #define CONFIG_SYS_MPC86xx_DDR2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC86xx_DMA_OFFSET	(0x21000)
+#define CONFIG_SYS_MPC86xx_DMA_OFFSET	0x21000
 #define CONFIG_SYS_MPC86xx_DMA_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC86xx_PIC_OFFSET	0x40000
+#define CONFIG_SYS_MPC8xxx_PIC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
+
 
 #define CONFIG_SYS_MPC86xx_PCI1_OFFSET		0x8000
 #ifdef CONFIG_MPC8610