Merge branch 'next' of /home/wd/git/u-boot/next

Conflicts:
	include/ppc4xx.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

56 files changed, 3800 insertions, 952 deletions

diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index ae2f6dc..37b06f3 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -38,7 +38,6 @@ COBJS-y += serial.o
 COBJS-y += speed.o
 COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
 COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o
-COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_logo_bmp.o
 COBJS-$(CONFIG_CMD_IDE) += ide.o
 COBJS-$(CONFIG_IIM) += iim.o
 COBJS-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c
index 9ef5609..fa4a0bc 100644
--- a/arch/powerpc/cpu/mpc512x/diu.c
+++ b/arch/powerpc/cpu/mpc512x/diu.c
@@ -36,12 +36,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_FSL_DIU_LOGO_BMP
-extern unsigned int FSL_Logo_BMP[];
-#else
-#define FSL_Logo_BMP NULL
-#endif
-
 static int xres, yres;
 
 void diu_set_pixel_clock(unsigned int pixclock)
@@ -64,28 +58,9 @@ void diu_set_pixel_clock(unsigned int pixclock)
 	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
 }
 
-char *valid_bmp(char *addr)
-{
-	unsigned long h_addr;
-	bd_t *bd = gd->bd;
-
-	h_addr = simple_strtoul(addr, NULL, 16);
-	if (h_addr < bd->bi_flashstart ||
-	    h_addr >= (bd->bi_flashstart + bd->bi_flashsize - 1)) {
-		printf("bmp addr %lx is not a valid flash address\n", h_addr);
-		return 0;
-	} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
-		printf("bmp addr is not a bmp\n");
-		return 0;
-	} else
-		return (char *)h_addr;
-}
-
 int mpc5121_diu_init(void)
 {
 	unsigned int pixel_format;
-	char *bmp = NULL;
-	char *bmp_env;
 
 #if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES)
 	xres = CONFIG_VIDEO_XRES;
@@ -97,47 +72,10 @@ int mpc5121_diu_init(void)
 	pixel_format = 0x88883316;
 
 	debug("mpc5121_diu_init\n");
-	bmp_env = getenv("diu_bmp_addr");
-	if (bmp_env) {
-		bmp = valid_bmp(bmp_env);
-	}
-	if (!bmp)
-		bmp = (char *)FSL_Logo_BMP;
-	return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp);
-}
-
-int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
-			     int flag, int argc, char * const argv[])
-{
-	unsigned int addr;
-
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	if (!strncmp(argv[1], "init", 4)) {
-#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
-		fsl_diu_clear_screen();
-		drv_video_init();
-#else
-		return mpc5121_diu_init();
-#endif
-	} else {
-		addr = simple_strtoul(argv[1], NULL, 16);
-		fsl_diu_clear_screen();
-		fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
-	}
 
-	return 0;
+	return fsl_diu_init(xres, pixel_format, 0);
 }
 
-U_BOOT_CMD(
-	diufb, CONFIG_SYS_MAXARGS, 1, mpc5121diu_init_show_bmp,
-	"Init or Display BMP file",
-	"init\n    - initialize DIU\n"
-	"addr\n    - display bmp at address 'addr'"
-	);
-
-
 #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
 
 /*
@@ -158,7 +96,7 @@ void *video_hw_init(void)
 
 	pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
 	pGD->winSizeX = xres;
-	pGD->winSizeY = yres - info->logo_height;
+	pGD->winSizeY = yres;
 	pGD->plnSizeX = pGD->winSizeX;
 	pGD->plnSizeY = pGD->winSizeY;
 
@@ -167,7 +105,7 @@ void *video_hw_init(void)
 
 	pGD->isaBase = 0;
 	pGD->pciBase = 0;
-	pGD->memSize = info->screen_size - info->logo_size;
+	pGD->memSize = info->screen_size;
 
 	/* Cursor Start Address */
 	pGD->dprBase = 0;
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 83cba93..f01c09a 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -126,6 +126,12 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 		SCCR_PCICM |
 #endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP1CM	/* PCIE1 clock mode */
+		SCCR_PCIEXP1CM |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP2CM	/* PCIE2 clock mode */
+		SCCR_PCIEXP2CM |
+#endif
 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 		SCCR_TSECCM |
 #endif
@@ -158,6 +164,12 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 		(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 #endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP1CM	/* PCIE1 clock mode */
+		(CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP2CM	/* PCIE2 clock mode */
+		(CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
+#endif
 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 		(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 #endif
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index a42b230..288d99f 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -133,7 +133,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
  * If fewer than three regions are requested, then the region
  * list is terminated with a region of size 0.
  */
-void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
 {
 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 	int i;
@@ -150,9 +150,9 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
 	/*
 	 * Release PCI RST Output signal.
 	 * Power on to RST high must be at least 100 ms as per PCI spec.
-	 * On warm boots only 1 ms is required.
+	 * On warm boots only 1 ms is required, but we play it safe.
 	 */
-	udelay(warmboot ? 1000 : 100000);
+	udelay(100000);
 
 	for (i = 0; i < num_buses; i++)
 		immr->pci_ctrl[i].gcr = 1;
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 77f8906..1771c48 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -30,6 +30,22 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define PCIE_MAX_BUSES 2
 
+static struct {
+	u32 base;
+	u32 size;
+} mpc83xx_pcie_cfg_space[] = {
+	{
+		.base = CONFIG_SYS_PCIE1_CFG_BASE,
+		.size = CONFIG_SYS_PCIE1_CFG_SIZE,
+	},
+#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
+	{
+		.base = CONFIG_SYS_PCIE2_CFG_BASE,
+		.size = CONFIG_SYS_PCIE2_CFG_SIZE,
+	},
+#endif
+};
+
 #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
 
 static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
@@ -124,10 +140,7 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 	hose->first_busno = pci_last_busno() + 1;
 	hose->last_busno = 0xff;
 
-	if (bus == 0)
-		hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE;
-	else
-		hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE;
+	hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
 
 	pci_set_ops(hose,
 			pcie_read_config_byte,
@@ -182,15 +195,9 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
 		PEX_CSB_OBCTRL_CFGWE);
 
 	out_win = &pex->bridge.pex_outbound_win[0];
-	if (bus) {
-		out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
-			CONFIG_SYS_PCIE2_CFG_SIZE);
-		out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE);
-	} else {
-		out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
-			CONFIG_SYS_PCIE1_CFG_SIZE);
-		out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE);
-	}
+	out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
+			mpc83xx_pcie_cfg_space[bus].size);
+	out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
 	out_le32(&out_win->tarl, 0);
 	out_le32(&out_win->tarh, 0);
 
@@ -301,16 +308,21 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
  * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
  * must have been set to cover all of the requested regions.
  */
-void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot)
+void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
 {
 	int i;
 
 	/*
 	 * Release PCI RST Output signal.
 	 * Power on to RST high must be at least 100 ms as per PCI spec.
-	 * On warm boots only 1 ms is required.
+	 * On warm boots only 1 ms is required, but we play it safe.
 	 */
-	udelay(warmboot ? 1000 : 100000);
+	udelay(100000);
+
+	if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
+		printf("Second PCIE host contoller not configured!\n");
+		num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
+	}
 
 	for (i = 0; i < num_buses; i++)
 		mpc83xx_pcie_init_bus(i, reg[i]);
diff --git a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
index f65cd88..a31b17e 100644
--- a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
@@ -45,7 +45,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <i2c.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 
 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
 
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
index 005315b..ec7291f 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
@@ -50,7 +50,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <i2c.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <asm/mmu.h>
 
 #include "ecc.h"
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index ff5ef5f..cf9d66d 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -41,7 +41,7 @@
 
 #include <common.h>
 #include <command.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/processor.h>
@@ -469,7 +469,7 @@ phys_size_t initdram(int board_type)
 	/*------------------------------------------------------------------
 	 * Reset the DDR-SDRAM controller.
 	 *-----------------------------------------------------------------*/
-	mtsdr(SDR0_SRST, (0x80000000 >> 10));
+	mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
 	mtsdr(SDR0_SRST, 0x00000000);
 
 	/*
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 2cfc37f..e90c93e 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -38,7 +38,7 @@
 #undef DEBUG
 
 #include <common.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <asm/io.h>
 #include <asm/processor.h>
 
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
index bfba952..80b0c1c 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
@@ -594,35 +594,35 @@ int __pci_pre_init(struct pci_controller *hose)
 	 * Set priority for all PLB3 devices to 0.
 	 * Set PLB3 arbiter to fair mode.
 	 */
-	mfsdr(SD0_AMP1, reg);
-	mtsdr(SD0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
-	reg = mfdcr(PLB3_ACR);
-	mtdcr(PLB3_ACR, reg | 0x80000000);
+	mfsdr(SDR0_AMP1, reg);
+	mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
+	reg = mfdcr(PLB3A0_ACR);
+	mtdcr(PLB3A0_ACR, reg | 0x80000000);
 
 	/*
 	 * Set priority for all PLB4 devices to 0.
 	 */
-	mfsdr(SD0_AMP0, reg);
-	mtsdr(SD0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
-	reg = mfdcr(PLB4_ACR) | 0xa0000000;
-	mtdcr(PLB4_ACR, reg);
+	mfsdr(SDR0_AMP0, reg);
+	mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
+	reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
+	mtdcr(PLB4A0_ACR, reg);
 
 	/*
 	 * Set Nebula PLB4 arbiter to fair mode.
 	 */
 	/* Segment0 */
-	reg = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
-	reg = (reg & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
-	reg = (reg & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
-	reg = (reg & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
-	mtdcr(PLB0_ACR, reg);
+	reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
+	reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
+	reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
+	reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
+	mtdcr(PLB4A0_ACR, reg);
 
 	/* Segment1 */
-	reg = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
-	reg = (reg & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
-	reg = (reg & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
-	reg = (reg & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
-	mtdcr(PLB1_ACR, reg);
+	reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
+	reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
+	reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
+	reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
+	mtdcr(PLB4A1_ACR, reg);
 
 #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
 	hose->fixup_irq = board_pci_fixup_irq;
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
index 10b58b7..b76890e 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
@@ -27,7 +27,7 @@
 
 #include <common.h>
 #include <pci.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/errno.h>
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
index e6ab570..2660aa8 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -49,15 +52,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <watchdog.h>
-#include <ppc4xx.h>
-
-#ifdef CONFIG_SERIAL_MULTI
-#include <serial.h>
-#endif
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-#include <malloc.h>
-#endif
+#include <asm/ppc4xx.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -66,24 +61,6 @@ DECLARE_GLOBAL_DATA_PTR;
     defined(CONFIG_405EX) || defined(CONFIG_440)
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART0_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
-#define UART1_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000400)
-#else
-#define UART0_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000200)
-#define UART1_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
-#endif
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART2_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
-#define UART3_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
-#endif
 
 #if defined(CONFIG_440GP)
 #define CR0_MASK        0x3fff0000
@@ -116,16 +93,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MTREG(a, d)	mtsdr(a, d)
 #endif /* #if defined(CONFIG_440GP) */
 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
-#define UART0_BASE      0xef600300
-#define UART1_BASE      0xef600400
 #define UCR0_MASK       0x0000007f
 #define UCR1_MASK       0x00007f00
 #define UCR0_UDIV_POS   0
 #define UCR1_UDIV_POS   8
 #define UDIV_MAX        127
 #elif defined(CONFIG_405EX)
-#define UART0_BASE	0xef600200
-#define UART1_BASE	0xef600300
+#define MFREG(a, d)	mfsdr(a, d)
+#define MTREG(a, d)	mtsdr(a, d)
 #define CR0_MASK	0x000000ff
 #define CR0_EXTCLK_ENA	0x00800000
 #define CR0_UDIV_POS	0
@@ -133,748 +108,198 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UART0_SDR	SDR0_UART0
 #define UART1_SDR	SDR0_UART1
 #else /* CONFIG_405GP || CONFIG_405CR */
-#define UART0_BASE      0xef600300
-#define UART1_BASE      0xef600400
 #define CR0_MASK        0x00001fff
 #define CR0_EXTCLK_ENA  0x000000c0
 #define CR0_UDIV_POS    1
 #define UDIV_MAX        32
 #endif
 
-/* using serial port 0 or 1 as U-Boot console ? */
-#if defined(CONFIG_UART1_CONSOLE)
-#define ACTING_UART0_BASE	UART1_BASE
-#define ACTING_UART1_BASE	UART0_BASE
-#else
-#define ACTING_UART0_BASE	UART0_BASE
-#define ACTING_UART1_BASE	UART1_BASE
-#endif
-
 #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 #error "External serial clock not supported on AMCC PPC405EP!"
 #endif
 
-#define UART_RBR    0x00
-#define UART_THR    0x00
-#define UART_IER    0x01
-#define UART_IIR    0x02
-#define UART_FCR    0x02
-#define UART_LCR    0x03
-#define UART_MCR    0x04
-#define UART_LSR    0x05
-#define UART_MSR    0x06
-#define UART_SCR    0x07
-#define UART_DLL    0x00
-#define UART_DLM    0x01
-
-/*-----------------------------------------------------------------------------+
-  | Line Status Register.
-  +-----------------------------------------------------------------------------*/
-#define asyncLSRDataReady1            0x01
-#define asyncLSROverrunError1         0x02
-#define asyncLSRParityError1          0x04
-#define asyncLSRFramingError1         0x08
-#define asyncLSRBreakInterrupt1       0x10
-#define asyncLSRTxHoldEmpty1          0x20
-#define asyncLSRTxShiftEmpty1         0x40
-#define asyncLSRRxFifoError1          0x80
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-/*-----------------------------------------------------------------------------+
-  | Fifo
-  +-----------------------------------------------------------------------------*/
-typedef struct {
-	char *rx_buffer;
-	ulong rx_put;
-	ulong rx_get;
-} serial_buffer_t;
-
-volatile static serial_buffer_t buf_info;
-#endif
-
-static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
-{
-	PPC4xx_SYS_INFO sys_info;
-	u8 val;
-
-	get_sys_info(&sys_info);
-
-	/* Correct UART frequency in bd-info struct now that
-	 * the UART divisor is available
-	 */
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
-	gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
-#else
-	gd->uart_clk = sys_info.freqUART / udiv;
-#endif
-
-	out_8((u8 *)base + UART_LCR, 0x80);	/* set DLAB bit */
-	out_8((u8 *)base + UART_DLL, bdiv);	/* set baudrate divisor */
-	out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
-	out_8((u8 *)base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out_8((u8 *)base + UART_FCR, 0x00);	/* disable FIFO */
-	out_8((u8 *)base + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in_8((u8 *)base + UART_LSR);	/* clear line status */
-	val = in_8((u8 *)base + UART_RBR);	/* read receive buffer */
-	out_8((u8 *)base + UART_SCR, 0x00);	/* set scratchpad */
-	out_8((u8 *)base + UART_IER, 0x00);	/* set interrupt enable reg */
-}
-
-#if (defined(CONFIG_440) || defined(CONFIG_405EX)) &&	\
-    !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
-static void serial_divs (int baudrate, unsigned long *pudiv,
-			 unsigned short *pbdiv)
+#if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) ||	\
+     defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
+/*
+ * For some SoC's, the cpu clock is on divider chain A, UART on
+ * divider chain B ... so cpu clock is irrelevant. Get the
+ * "optimized" values that are subject to the 1/2 opb clock
+ * constraint.
+ */
+static u16 serial_bdiv(int baudrate, u32 *udiv)
 {
 	sys_info_t sysinfo;
-	unsigned long div;		/* total divisor udiv * bdiv */
-	unsigned long umin;		/* minimum udiv	*/
-	unsigned short diff;		/* smallest diff */
-	unsigned long udiv;		/* best udiv */
-	unsigned short idiff;		/* current diff */
-	unsigned short ibdiv;		/* current bdiv */
-	unsigned long i;
-	unsigned long est;		/* current estimate */
+	u32 div;		/* total divisor udiv * bdiv */
+	u32 umin;		/* minimum udiv	*/
+	u16 diff;		/* smallest diff */
+	u16 idiff;		/* current diff */
+	u16 ibdiv;		/* current bdiv */
+	u32 i;
+	u32 est;		/* current estimate */
+	u32 max;
+#if defined(CONFIG_405EZ)
+	u32 cpr_pllc;
+	u32 plloutb;
+	u32 reg;
+#endif
 
 	get_sys_info(&sysinfo);
 
-	udiv = 32;			/* Assume lowest possible serial clk */
-	div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
-	umin = sysinfo.pllOpbDiv << 1;	/* 2 x OPB divisor */
-	diff = 32;			/* highest possible */
-
-	/* i is the test udiv value -- start with the largest
-	 * possible (32) to minimize serial clock and constrain
-	 * search to umin.
-	 */
-	for (i = 32; i > umin; i--) {
-		ibdiv = div / i;
-		est = i * ibdiv;
-		idiff = (est > div) ? (est-div) : (div-est);
-		if (idiff == 0) {
-			udiv = i;
-			break;      /* can't do better */
-		} else if (idiff < diff) {
-			udiv = i;       /* best so far */
-			diff = idiff;   /* update lowest diff*/
-		}
-	}
-
-	*pudiv = udiv;
-	*pbdiv = div / udiv;
-}
-
-#elif defined(CONFIG_405EZ)
-
-static void serial_divs (int baudrate, unsigned long *pudiv,
-			 unsigned short *pbdiv)
-{
-	sys_info_t sysinfo;
-	unsigned long div;		/* total divisor udiv * bdiv */
-	unsigned long umin;		/* minimum udiv	*/
-	unsigned short diff;		/* smallest diff */
-	unsigned long udiv;		/* best udiv */
-	unsigned short idiff;		/* current diff */
-	unsigned short ibdiv;		/* current bdiv */
-	unsigned long i;
-	unsigned long est;		/* current estimate */
-	unsigned long plloutb;
-	unsigned long cpr_pllc;
-	u32 reg;
-
+#if defined(CONFIG_405EZ)
 	/* check the pll feedback source */
 	mfcpr(CPR0_PLLC, cpr_pllc);
-
-	get_sys_info(&sysinfo);
-
 	plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
 					   sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
 		    sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
-	udiv = 256;			/* Assume lowest possible serial clk */
 	div = plloutb / (16 * baudrate); /* total divisor */
 	umin = (plloutb / get_OPB_freq()) << 1;	/* 2 x OPB divisor */
-	diff = 256;			/* highest possible */
+	max = 256;			/* highest possible */
+#else /* 405EZ */
+	div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
+	umin = sysinfo.pllOpbDiv << 1;	/* 2 x OPB divisor */
+	max = 32;			/* highest possible */
+#endif /* 405EZ */
+
+	*udiv = diff = max;
 
-	/* i is the test udiv value -- start with the largest
-	 * possible (256) to minimize serial clock and constrain
+	/*
+	 * i is the test udiv value -- start with the largest
+	 * possible (max) to minimize serial clock and constrain
 	 * search to umin.
 	 */
-	for (i = 256; i > umin; i--) {
+	for (i = max; i > umin; i--) {
 		ibdiv = div / i;
 		est = i * ibdiv;
-		idiff = (est > div) ? (est-div) : (div-est);
+		idiff = (est > div) ? (est - div) : (div - est);
 		if (idiff == 0) {
-			udiv = i;
-			break;      /* can't do better */
+			*udiv = i;
+			break;		/* can't do better */
 		} else if (idiff < diff) {
-			udiv = i;       /* best so far */
-			diff = idiff;   /* update lowest diff*/
+			*udiv = i;	/* best so far */
+			diff = idiff;	/* update lowest diff*/
 		}
 	}
 
-	*pudiv = udiv;
-	mfcpr(CPC0_PERD0, reg);
+#if defined(CONFIG_405EZ)
+	mfcpr(CPR0_PERD0, reg);
 	reg &= ~0x0000ffff;
-	reg |= ((udiv - 0) << 8) | (udiv - 0);
-	mtcpr(CPC0_PERD0, reg);
-	*pbdiv = div / udiv;
+	reg |= ((*udiv - 0) << 8) | (*udiv - 0);
+	mtcpr(CPR0_PERD0, reg);
+#endif
+
+	return div / *udiv;
 }
-#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
+#endif /* #if (defined(CONFIG_405EP) ... */
 
 /*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
+ * This function returns the UART clock used by the common
+ * NS16550 driver. Additionally the SoC internal divisors for
+ * optimal UART baudrate are configured.
  */
-
-#if defined(CONFIG_440)
-int serial_init_dev(unsigned long base)
+int get_serial_clock(void)
 {
-	unsigned long reg;
-	unsigned long udiv;
-	unsigned short bdiv;
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
-	unsigned long tmp;
-#endif
-
-	MFREG(UART0_SDR, reg);
-	reg &= ~CR0_MASK;
-
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
-	reg |= CR0_EXTCLK_ENA;
-	udiv = 1;
-	tmp  = gd->baudrate * 16;
-	bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
-#else
-	/* For 440, the cpu clock is on divider chain A, UART on divider
-	 * chain B ... so cpu clock is irrelevant. Get the "optimized"
-	 * values that are subject to the 1/2 opb clock constraint
-	 */
-	serial_divs (gd->baudrate, &udiv, &bdiv);
+	u32 clk;
+	u32 udiv;
+#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || defined(CONFIG_405GP)
+	u32 tmp;
 #endif
-
-	reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;	/* set the UART divisor */
-
-	/*
-	 * Configure input clock to baudrate generator for all
-	 * available serial ports here
-	 */
-	MTREG(UART0_SDR, reg);
-#if defined(UART1_SDR)
-	MTREG(UART1_SDR, reg);
-#endif
-#if defined(UART2_SDR)
-	MTREG(UART2_SDR, reg);
-#endif
-#if defined(UART3_SDR)
-	MTREG(UART3_SDR, reg);
+#if !defined(CONFIG_405EZ)
+	u32 reg;
 #endif
-
-	serial_init_common(base, udiv, bdiv);
-
-	return (0);
-}
-
-#else /* !defined(CONFIG_440) */
-
-int serial_init_dev (unsigned long base)
-{
-	unsigned long reg;
-	unsigned long tmp;
-	unsigned long clk;
-	unsigned long udiv;
-	unsigned short bdiv;
-
-#ifdef CONFIG_405EX
-	clk = tmp = 0;
-	mfsdr(UART0_SDR, reg);
-	reg &= ~CR0_MASK;
-#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
-	reg |= CR0_EXTCLK_ENA;
-	udiv = 1;
-	tmp  = gd->baudrate * 16;
-	bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
-#else
-	serial_divs(gd->baudrate, &udiv, &bdiv);
+#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
+	PPC4xx_SYS_INFO sys_info;
 #endif
-	reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;  /* set the UART divisor */
 
 	/*
-	 * Configure input clock to baudrate generator for all
-	 * available serial ports here
+	 * Programming of the internal divisors is SoC specific.
+	 * Let's handle this in some #ifdef's for the SoC's.
 	 */
-	mtsdr(UART0_SDR, reg);
-
-#if defined(UART1_SDR)
-	mtsdr(UART1_SDR, reg);
-#endif
 
-#elif defined(CONFIG_405EZ)
-	serial_divs(gd->baudrate, &udiv, &bdiv);
-	clk = tmp = reg = 0;
-#else
-#ifdef CONFIG_405EP
-	reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
-	clk = gd->cpu_clk;
-	tmp = CONFIG_SYS_BASE_BAUD * 16;
-	udiv = (clk + tmp / 2) / tmp;
-	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
-		udiv = UDIV_MAX;
-	reg |= (udiv) << UCR0_UDIV_POS;	        /* set the UART divisor */
-	reg |= (udiv) << UCR1_UDIV_POS;	        /* set the UART divisor */
-	mtdcr (CPC0_UCR, reg);
-#else /* CONFIG_405EP */
+#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
+	tmp = 0;
 	reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 	udiv = 1;
 	reg |= CR0_EXTCLK_ENA;
-#else
+#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 	clk = gd->cpu_clk;
 #ifdef CONFIG_SYS_405_UART_ERRATA_59
 	udiv = 31;			/* Errata 59: stuck at 31 */
-#else
+#else /* CONFIG_SYS_405_UART_ERRATA_59 */
 	tmp = CONFIG_SYS_BASE_BAUD * 16;
 	udiv = (clk + tmp / 2) / tmp;
 	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 		udiv = UDIV_MAX;
-#endif
-#endif
+#endif /* CONFIG_SYS_405_UART_ERRATA_59 */
+#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
 	mtdcr (CPC0_CR0, reg);
-#endif /* CONFIG_405EP */
-	tmp = gd->baudrate * udiv * 16;
-	bdiv = (clk + tmp / 2) / tmp;
-#endif /* CONFIG_405EX */
-
-	serial_init_common(base, udiv, bdiv);
-
-	return (0);
-}
-
-#endif /* if defined(CONFIG_440) */
-
-void serial_setbrg_dev(unsigned long base)
-{
-	serial_init_dev(base);
-}
-
-void serial_putc_dev(unsigned long base, const char c)
-{
-	int i;
-
-	if (c == '\n')
-		serial_putc_dev(base, '\r');
-
-	/* check THRE bit, wait for transmiter available */
-	for (i = 1; i < 3500; i++) {
-		if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20)
-			break;
-		udelay (100);
-	}
-
-	out_8((u8 *)base + UART_THR, c);	/* put character out */
-}
-
-void serial_puts_dev (unsigned long base, const char *s)
-{
-	while (*s)
-		serial_putc_dev (base, *s++);
-}
-
-int serial_getc_dev (unsigned long base)
-{
-	unsigned char status = 0;
-
-	while (1) {
-#if defined(CONFIG_HW_WATCHDOG)
-		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-#endif	/* CONFIG_HW_WATCHDOG */
-
-		status = in_8((u8 *)base + UART_LSR);
-		if ((status & asyncLSRDataReady1) != 0x0)
-			break;
-
-		if ((status & ( asyncLSRFramingError1 |
-				asyncLSROverrunError1 |
-				asyncLSRParityError1  |
-				asyncLSRBreakInterrupt1 )) != 0) {
-			out_8((u8 *)base + UART_LSR,
-			      asyncLSRFramingError1 |
-			      asyncLSROverrunError1 |
-			      asyncLSRParityError1  |
-			      asyncLSRBreakInterrupt1);
-		}
-	}
-
-	return (0x000000ff & (int) in_8((u8 *)base));
-}
-
-int serial_tstc_dev (unsigned long base)
-{
-	unsigned char status;
-
-	status = in_8((u8 *)base + UART_LSR);
-	if ((status & asyncLSRDataReady1) != 0x0)
-		return (1);
-
-	if ((status & ( asyncLSRFramingError1 |
-			asyncLSROverrunError1 |
-			asyncLSRParityError1  |
-			asyncLSRBreakInterrupt1 )) != 0) {
-		out_8((u8 *)base + UART_LSR,
-		      asyncLSRFramingError1 |
-		      asyncLSROverrunError1 |
-		      asyncLSRParityError1  |
-		      asyncLSRBreakInterrupt1);
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-
-void serial_isr (void *arg)
-{
-	int space;
-	int c;
-	const int rx_get = buf_info.rx_get;
-	int rx_put = buf_info.rx_put;
-
-	if (rx_get <= rx_put)
-		space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
-	else
-		space = rx_get - rx_put;
-
-	while (serial_tstc_dev (ACTING_UART0_BASE)) {
-		c = serial_getc_dev (ACTING_UART0_BASE);
-		if (space) {
-			buf_info.rx_buffer[rx_put++] = c;
-			space--;
-		}
-		if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
-			rx_put = 0;
-		if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
-			/* Stop flow by setting RTS inactive */
-			out_8((u8 *)ACTING_UART0_BASE + UART_MCR,
-			      in_8((u8 *)ACTING_UART0_BASE + UART_MCR) &
-			      (0xFF ^ 0x02));
-		}
-	}
-	buf_info.rx_put = rx_put;
-}
-
-void serial_buffered_init (void)
-{
-	serial_puts ("Switching to interrupt driven serial input mode.\n");
-	buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
-	buf_info.rx_put = 0;
-	buf_info.rx_get = 0;
-
-	if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)
-		serial_puts ("Check CTS signal present on serial port: OK.\n");
-	else
-		serial_puts ("WARNING: CTS signal not present on serial port.\n");
-
-	irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
-			      serial_isr /*interrupt_handler_t *handler */ ,
-			      (void *) &buf_info /*void *arg */ );
-
-	/* Enable "RX Data Available" Interrupt on UART */
-	out_8(ACTING_UART0_BASE + UART_IER, 0x01);
-	/* Set DTR active */
-	out_8(ACTING_UART0_BASE + UART_MCR,
-	      in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01);
-	/* Start flow by setting RTS active */
-	out_8(ACTING_UART0_BASE + UART_MCR,
-	      in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
-	/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
-	out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
-}
-
-void serial_buffered_putc (const char c)
-{
-	/* Wait for CTS */
-#if defined(CONFIG_HW_WATCHDOG)
-	while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10))
-		WATCHDOG_RESET ();
-#else
-	while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10));
-#endif
-	serial_putc (c);
-}
-
-void serial_buffered_puts (const char *s)
-{
-	serial_puts (s);
-}
-
-int serial_buffered_getc (void)
-{
-	int space;
-	int c;
-	int rx_get = buf_info.rx_get;
-	int rx_put;
-
-#if defined(CONFIG_HW_WATCHDOG)
-	while (rx_get == buf_info.rx_put)
-		WATCHDOG_RESET ();
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+	clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 #else
-	while (rx_get == buf_info.rx_put);
+	clk = CONFIG_SYS_BASE_BAUD * 16;
 #endif
-	c = buf_info.rx_buffer[rx_get++];
-	if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
-		rx_get = 0;
-	buf_info.rx_get = rx_get;
-
-	rx_put = buf_info.rx_put;
-	if (rx_get <= rx_put)
-		space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
-	else
-		space = rx_get - rx_put;
-
-	if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
-		/* Start flow by setting RTS active */
-		out_8(ACTING_UART0_BASE + UART_MCR,
-		      in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
-	}
+#endif /* CONFIG_405CR */
 
-	return c;
-}
+#if defined(CONFIG_405EP)
+	reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
+	clk = gd->cpu_clk;
+	tmp = CONFIG_SYS_BASE_BAUD * 16;
+	udiv = (clk + tmp / 2) / tmp;
+	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
+		udiv = UDIV_MAX;
+	reg |= udiv << UCR0_UDIV_POS;	        /* set the UART divisor */
+	reg |= udiv << UCR1_UDIV_POS;	        /* set the UART divisor */
+	mtdcr(CPC0_UCR, reg);
+	clk = CONFIG_SYS_BASE_BAUD * 16;
+#endif /* CONFIG_405EP */
 
-int serial_buffered_tstc (void)
-{
-	return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
-}
+#if defined(CONFIG_405EX) || defined(CONFIG_440)
+	MFREG(UART0_SDR, reg);
+	reg &= ~CR0_MASK;
 
-#endif	/* CONFIG_SERIAL_SOFTWARE_FIFO */
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+	reg |= CR0_EXTCLK_ENA;
+	udiv = 1;
+	clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
+#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
+	clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
+#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
 
-#if defined(CONFIG_CMD_KGDB)
-/*
-  AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
-  number 0 or number 1
-  - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
-  configuration has been already done
-  - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
-  configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
-*/
-#if (CONFIG_KGDB_SER_INDEX & 2)
-void kgdb_serial_init (void)
-{
-	u8 val;
-	u16 br_reg;
+	reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;	/* set the UART divisor */
 
-	get_clocks ();
-	br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
-		  5) / 10;
 	/*
-	 * Init onboard 16550 UART
+	 * Configure input clock to baudrate generator for all
+	 * available serial ports here
 	 */
-	out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
-	out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
-	out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03);	/* line control 8 bits no parity */
-	out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR);		/* clear line status */
-	val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR);		/* read receive buffer */
-	out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
-}
-
-void putDebugChar (const char c)
-{
-	if (c == '\n')
-		serial_putc ('\r');
-
-	out_8((u8 *)ACTING_UART1_BASE + UART_THR, c);	/* put character out */
-
-	/* check THRE bit, wait for transfer done */
-	while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
-}
-
-void putDebugStr (const char *s)
-{
-	while (*s)
-		serial_putc (*s++);
-}
-
-int getDebugChar (void)
-{
-	unsigned char status = 0;
-
-	while (1) {
-		status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR);
-		if ((status & asyncLSRDataReady1) != 0x0)
-			break;
-
-		if ((status & (asyncLSRFramingError1 |
-			       asyncLSROverrunError1 |
-			       asyncLSRParityError1  |
-			       asyncLSRBreakInterrupt1 )) != 0) {
-			out_8((u8 *)ACTING_UART1_BASE + UART_LSR,
-			      asyncLSRFramingError1 |
-			      asyncLSROverrunError1 |
-			      asyncLSRParityError1  |
-			      asyncLSRBreakInterrupt1);
-		}
-	}
-
-	return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE));
-}
-
-void kgdb_interruptible (int yes)
-{
-	return;
-}
-
-#else	/* ! (CONFIG_KGDB_SER_INDEX & 2) */
-
-void kgdb_serial_init (void)
-{
-	serial_printf ("[on serial] ");
-}
-
-void putDebugChar (int c)
-{
-	serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
-	serial_puts (str);
-}
-
-int getDebugChar (void)
-{
-	return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
-	return;
-}
-#endif	/* (CONFIG_KGDB_SER_INDEX & 2) */
+	MTREG(UART0_SDR, reg);
+#if defined(UART1_SDR)
+	MTREG(UART1_SDR, reg);
 #endif
+#if defined(UART2_SDR)
+	MTREG(UART2_SDR, reg);
+#endif
+#if defined(UART3_SDR)
+	MTREG(UART3_SDR, reg);
+#endif
+#endif /* CONFIG_405EX ... */
 
+#if defined(CONFIG_405EZ)
+	clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
+#endif /* CONFIG_405EZ */
 
-#if defined(CONFIG_SERIAL_MULTI)
-int serial0_init(void)
-{
-	return (serial_init_dev(UART0_BASE));
-}
-
-int serial1_init(void)
-{
-	return (serial_init_dev(UART1_BASE));
-}
-
-void serial0_setbrg (void)
-{
-	serial_setbrg_dev(UART0_BASE);
-}
-
-void serial1_setbrg (void)
-{
-	serial_setbrg_dev(UART1_BASE);
-}
-
-void serial0_putc(const char c)
-{
-	serial_putc_dev(UART0_BASE,c);
-}
-
-void serial1_putc(const char c)
-{
-	serial_putc_dev(UART1_BASE, c);
-}
-
-void serial0_puts(const char *s)
-{
-	serial_puts_dev(UART0_BASE, s);
-}
-
-void serial1_puts(const char *s)
-{
-	serial_puts_dev(UART1_BASE, s);
-}
-
-int serial0_getc(void)
-{
-	return(serial_getc_dev(UART0_BASE));
-}
-
-int serial1_getc(void)
-{
-	return(serial_getc_dev(UART1_BASE));
-}
-
-int serial0_tstc(void)
-{
-	return (serial_tstc_dev(UART0_BASE));
-}
-
-int serial1_tstc(void)
-{
-	return (serial_tstc_dev(UART1_BASE));
-}
-
-struct serial_device serial0_device =
-{
-	"serial0",
-	"UART0",
-	serial0_init,
-	NULL,
-	serial0_setbrg,
-	serial0_getc,
-	serial0_tstc,
-	serial0_putc,
-	serial0_puts,
-};
-
-struct serial_device serial1_device =
-{
-	"serial1",
-	"UART1",
-	serial1_init,
-	NULL,
-	serial1_setbrg,
-	serial1_getc,
-	serial1_tstc,
-	serial1_putc,
-	serial1_puts,
-};
+	/*
+	 * Correct UART frequency in bd-info struct now that
+	 * the UART divisor is available
+	 */
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+	gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 #else
-/*
- * Wrapper functions
- */
-int serial_init(void)
-{
-	return serial_init_dev(ACTING_UART0_BASE);
-}
-
-void serial_setbrg(void)
-{
-	serial_setbrg_dev(ACTING_UART0_BASE);
-}
-
-void serial_putc(const char c)
-{
-	serial_putc_dev(ACTING_UART0_BASE, c);
-}
-
-void serial_puts(const char *s)
-{
-	serial_puts_dev(ACTING_UART0_BASE, s);
-}
-
-int serial_getc(void)
-{
-	return serial_getc_dev(ACTING_UART0_BASE);
-}
+	get_sys_info(&sys_info);
+	gd->uart_clk = sys_info.freqUART / udiv;
+#endif
 
-int serial_tstc(void)
-{
-	return serial_tstc_dev(ACTING_UART0_BASE);
+	return clk;
 }
-#endif /* CONFIG_SERIAL_MULTI */
-
 #endif	/* CONFIG_405GP || CONFIG_405CR */
diff --git a/arch/powerpc/cpu/ppc4xx/cache.S b/arch/powerpc/cpu/ppc4xx/cache.S
index 269716f..757d7da 100644
--- a/arch/powerpc/cpu/ppc4xx/cache.S
+++ b/arch/powerpc/cpu/ppc4xx/cache.S
@@ -14,7 +14,7 @@
 
 #include <config.h>
 #include <config.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/cache.h>
diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
index b4eac40..fd81b70 100644
--- a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
+++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
@@ -23,7 +23,7 @@
  */
 
 #include <common.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/cache.h>
diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 851065c..6009b0c 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -35,7 +35,7 @@
 #include <watchdog.h>
 #include <command.h>
 #include <asm/cache.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -98,8 +98,8 @@ int pci_arbiter_enabled(void)
 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long val;
 
-	mfsdr(SDR0_XCR, val);
-	return (val & 0x80000000);
+	mfsdr(SDR0_XCR0, val);
+	return (val & SDR0_XCR0_PAE_MASK);
 #endif
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@@ -107,7 +107,7 @@ int pci_arbiter_enabled(void)
 	unsigned long val;
 
 	mfsdr(SDR0_PCI0, val);
-	return (val & 0x80000000);
+	return (val & SDR0_PCI0_PAE_MASK);
 #endif
 }
 #endif
@@ -262,7 +262,7 @@ static int bootstrap_option(void)
 #endif /* SDR0_PINSTP_SHIFT */
 
 
-#if defined(CONFIG_440)
+#if defined(CONFIG_440GP)
 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
 {
 	/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
@@ -276,7 +276,7 @@ static int do_chip_reset (unsigned long sys0, unsigned long sys1)
 
 	return 1;
 }
-#endif
+#endif /* CONFIG_440GP */
 
 
 int checkcpu (void)
@@ -303,122 +303,113 @@ int checkcpu (void)
 	get_sys_info(&sys_info);
 
 #if defined(CONFIG_XILINX_440)
-	puts("IBM PowerPC 4");
+	puts("IBM PowerPC ");
 #else
-	puts("AMCC PowerPC 4");
-#endif
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
-    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
-    defined(CONFIG_405EX)
-	puts("05");
-#endif
-#if defined(CONFIG_440)
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	puts("60");
-#else
-	puts("40");
-#endif
+	puts("AMCC PowerPC ");
 #endif
 
 	switch (pvr) {
+
+#if !defined(CONFIG_440)
 	case PVR_405GP_RB:
-		puts("GP Rev. B");
+		puts("405GP Rev. B");
 		break;
 
 	case PVR_405GP_RC:
-		puts("GP Rev. C");
+		puts("405GP Rev. C");
 		break;
 
 	case PVR_405GP_RD:
-		puts("GP Rev. D");
+		puts("405GP Rev. D");
 		break;
 
 #ifdef CONFIG_405GP
 	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
-		puts("GP Rev. E");
+		puts("405GP Rev. E");
 		break;
 #endif
 
 	case PVR_405CR_RA:
-		puts("CR Rev. A");
+		puts("405CR Rev. A");
 		break;
 
 	case PVR_405CR_RB:
-		puts("CR Rev. B");
+		puts("405CR Rev. B");
 		break;
 
 #ifdef CONFIG_405CR
 	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
-		puts("CR Rev. C");
+		puts("405CR Rev. C");
 		break;
 #endif
 
 	case PVR_405GPR_RB:
-		puts("GPr Rev. B");
+		puts("405GPr Rev. B");
 		break;
 
 	case PVR_405EP_RB:
-		puts("EP Rev. B");
+		puts("405EP Rev. B");
 		break;
 
 	case PVR_405EZ_RA:
-		puts("EZ Rev. A");
+		puts("405EZ Rev. A");
 		break;
 
 	case PVR_405EX1_RA:
-		puts("EX Rev. A");
+		puts("405EX Rev. A");
 		strcpy(addstr, "Security support");
 		break;
 
 	case PVR_405EXR2_RA:
-		puts("EXr Rev. A");
+		puts("405EXr Rev. A");
 		strcpy(addstr, "No Security support");
 		break;
 
 	case PVR_405EX1_RC:
-		puts("EX Rev. C");
+		puts("405EX Rev. C");
 		strcpy(addstr, "Security support");
 		break;
 
 	case PVR_405EX2_RC:
-		puts("EX Rev. C");
+		puts("405EX Rev. C");
 		strcpy(addstr, "No Security support");
 		break;
 
 	case PVR_405EXR1_RC:
-		puts("EXr Rev. C");
+		puts("405EXr Rev. C");
 		strcpy(addstr, "Security support");
 		break;
 
 	case PVR_405EXR2_RC:
-		puts("EXr Rev. C");
+		puts("405EXr Rev. C");
 		strcpy(addstr, "No Security support");
 		break;
 
 	case PVR_405EX1_RD:
-		puts("EX Rev. D");
+		puts("405EX Rev. D");
 		strcpy(addstr, "Security support");
 		break;
 
 	case PVR_405EX2_RD:
-		puts("EX Rev. D");
+		puts("405EX Rev. D");
 		strcpy(addstr, "No Security support");
 		break;
 
 	case PVR_405EXR1_RD:
-		puts("EXr Rev. D");
+		puts("405EXr Rev. D");
 		strcpy(addstr, "Security support");
 		break;
 
 	case PVR_405EXR2_RD:
-		puts("EXr Rev. D");
+		puts("405EXr Rev. D");
 		strcpy(addstr, "No Security support");
 		break;
 
-#if defined(CONFIG_440)
+#else /* CONFIG_440 */
+
+#if defined(CONFIG_440GP)
 	case PVR_440GP_RB:
-		puts("GP Rev. B");
+		puts("440GP Rev. B");
 		/* See errata 1.12: CHIP_4 */
 		if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
 		    (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
@@ -431,127 +422,127 @@ int checkcpu (void)
 		break;
 
 	case PVR_440GP_RC:
-		puts("GP Rev. C");
+		puts("440GP Rev. C");
 		break;
+#endif /* CONFIG_440GP */
 
 	case PVR_440GX_RA:
-		puts("GX Rev. A");
+		puts("440GX Rev. A");
 		break;
 
 	case PVR_440GX_RB:
-		puts("GX Rev. B");
+		puts("440GX Rev. B");
 		break;
 
 	case PVR_440GX_RC:
-		puts("GX Rev. C");
+		puts("440GX Rev. C");
 		break;
 
 	case PVR_440GX_RF:
-		puts("GX Rev. F");
+		puts("440GX Rev. F");
 		break;
 
 	case PVR_440EP_RA:
-		puts("EP Rev. A");
+		puts("440EP Rev. A");
 		break;
 
 #ifdef CONFIG_440EP
 	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
-		puts("EP Rev. B");
+		puts("440EP Rev. B");
 		break;
 
 	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
-		puts("EP Rev. C");
+		puts("440EP Rev. C");
 		break;
 #endif /*  CONFIG_440EP */
 
 #ifdef CONFIG_440GR
 	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
-		puts("GR Rev. A");
+		puts("440GR Rev. A");
 		break;
 
 	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
-		puts("GR Rev. B");
+		puts("440GR Rev. B");
 		break;
 #endif /* CONFIG_440GR */
-#endif /* CONFIG_440 */
 
 #ifdef CONFIG_440EPX
 	case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
-		puts("EPx Rev. A");
+		puts("440EPx Rev. A");
 		strcpy(addstr, "Security/Kasumi support");
 		break;
 
 	case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
-		puts("EPx Rev. A");
+		puts("440EPx Rev. A");
 		strcpy(addstr, "No Security/Kasumi support");
 		break;
 #endif /* CONFIG_440EPX */
 
 #ifdef CONFIG_440GRX
 	case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
-		puts("GRx Rev. A");
+		puts("440GRx Rev. A");
 		strcpy(addstr, "Security/Kasumi support");
 		break;
 
 	case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
-		puts("GRx Rev. A");
+		puts("440GRx Rev. A");
 		strcpy(addstr, "No Security/Kasumi support");
 		break;
 #endif /* CONFIG_440GRX */
 
 	case PVR_440SP_6_RAB:
-		puts("SP Rev. A/B");
+		puts("440SP Rev. A/B");
 		strcpy(addstr, "RAID 6 support");
 		break;
 
 	case PVR_440SP_RAB:
-		puts("SP Rev. A/B");
+		puts("440SP Rev. A/B");
 		strcpy(addstr, "No RAID 6 support");
 		break;
 
 	case PVR_440SP_6_RC:
-		puts("SP Rev. C");
+		puts("440SP Rev. C");
 		strcpy(addstr, "RAID 6 support");
 		break;
 
 	case PVR_440SP_RC:
-		puts("SP Rev. C");
+		puts("440SP Rev. C");
 		strcpy(addstr, "No RAID 6 support");
 		break;
 
 	case PVR_440SPe_6_RA:
-		puts("SPe Rev. A");
+		puts("440SPe Rev. A");
 		strcpy(addstr, "RAID 6 support");
 		break;
 
 	case PVR_440SPe_RA:
-		puts("SPe Rev. A");
+		puts("440SPe Rev. A");
 		strcpy(addstr, "No RAID 6 support");
 		break;
 
 	case PVR_440SPe_6_RB:
-		puts("SPe Rev. B");
+		puts("440SPe Rev. B");
 		strcpy(addstr, "RAID 6 support");
 		break;
 
 	case PVR_440SPe_RB:
-		puts("SPe Rev. B");
+		puts("440SPe Rev. B");
 		strcpy(addstr, "No RAID 6 support");
 		break;
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	case PVR_460EX_RA:
-		puts("EX Rev. A");
+		puts("460EX Rev. A");
 		strcpy(addstr, "No Security/Kasumi support");
 		break;
 
 	case PVR_460EX_SE_RA:
-		puts("EX Rev. A");
+		puts("460EX Rev. A");
 		strcpy(addstr, "Security/Kasumi support");
 		break;
 
 	case PVR_460EX_RB:
-		puts("EX Rev. B");
+		puts("460EX Rev. B");
 		mfsdr(SDR0_ECID3, reg);
 		if (reg & 0x00100000)
 			strcpy(addstr, "No Security/Kasumi support");
@@ -560,17 +551,17 @@ int checkcpu (void)
 		break;
 
 	case PVR_460GT_RA:
-		puts("GT Rev. A");
+		puts("460GT Rev. A");
 		strcpy(addstr, "No Security/Kasumi support");
 		break;
 
 	case PVR_460GT_SE_RA:
-		puts("GT Rev. A");
+		puts("460GT Rev. A");
 		strcpy(addstr, "Security/Kasumi support");
 		break;
 
 	case PVR_460GT_RB:
-		puts("GT Rev. B");
+		puts("460GT Rev. B");
 		mfsdr(SDR0_ECID3, reg);
 		if (reg & 0x00100000)
 			strcpy(addstr, "No Security/Kasumi support");
@@ -580,28 +571,29 @@ int checkcpu (void)
 #endif
 
 	case PVR_460SX_RA:
-		puts("SX Rev. A");
+		puts("460SX Rev. A");
 		strcpy(addstr, "Security support");
 		break;
 
 	case PVR_460SX_RA_V1:
-		puts("SX Rev. A");
+		puts("460SX Rev. A");
 		strcpy(addstr, "No Security support");
 		break;
 
 	case PVR_460GX_RA:
-		puts("GX Rev. A");
+		puts("460GX Rev. A");
 		strcpy(addstr, "Security support");
 		break;
 
 	case PVR_460GX_RA_V1:
-		puts("GX Rev. A");
+		puts("460GX Rev. A");
 		strcpy(addstr, "No Security support");
 		break;
 
 	case PVR_VIRTEX5:
-		puts("x5 VIRTEX5");
+		puts("440x5 VIRTEX5");
 		break;
+#endif /* CONFIG_440 */
 
 	default:
 		printf (" UNKNOWN (PVR=%08x)", pvr);
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index b31bd0b..d54b30e 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -23,10 +23,10 @@
 
 #include <common.h>
 #include <watchdog.h>
-#include <ppc4xx_enet.h>
+#include <asm/ppc4xx-emac.h>
 #include <asm/processor.h>
-#include <asm/gpio.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/ppc4xx.h>
 
 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
 DECLARE_GLOBAL_DATA_PTR;
@@ -266,7 +266,7 @@ cpu_init_f (void)
 	/*
 	 * Set EMAC noise filter bits
 	 */
-	mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
+	mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE);
 #endif /* CONFIG_405EP */
 
 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
@@ -397,10 +397,10 @@ cpu_init_f (void)
 	/*
 	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 	 */
-	mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) |
-	      PLB0_ACR_RDP_4DEEP);
-	mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) |
-	      PLB1_ACR_RDP_4DEEP);
+	mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
+	      PLB4Ax_ACR_RDP_4DEEP);
+	mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
+	      PLB4Ax_ACR_RDP_4DEEP);
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 }
 
diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S
index 93465a3..e668e05 100644
--- a/arch/powerpc/cpu/ppc4xx/dcr.S
+++ b/arch/powerpc/cpu/ppc4xx/dcr.S
@@ -24,7 +24,7 @@
 
 #if defined(CONFIG_4xx) && defined(CONFIG_CMD_SETGETDCR)
 
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 
 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
 
diff --git a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c
index 03b8d3c..9bba0ca 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c
@@ -36,7 +36,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 /*-----------------------------------------------------------------------------+
diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
index 080ea0a..c35b113 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
@@ -40,7 +40,7 @@
 
 #include <common.h>
 #include <command.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/processor.h>
diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c
index 49f28d9..7fe5dbb 100644
--- a/arch/powerpc/cpu/ppc4xx/ecc.c
+++ b/arch/powerpc/cpu/ppc4xx/ecc.c
@@ -37,7 +37,7 @@
  */
 
 #include <common.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/processor.h>
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index e99b2b0..5ddb880 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -25,7 +25,7 @@
 #include <watchdog.h>
 #include <command.h>
 #include <asm/cache.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 #include <libfdt.h>
diff --git a/arch/powerpc/cpu/ppc4xx/gpio.c b/arch/powerpc/cpu/ppc4xx/gpio.c
index c0d351a..20f0572 100644
--- a/arch/powerpc/cpu/ppc4xx/gpio.c
+++ b/arch/powerpc/cpu/ppc4xx/gpio.c
@@ -24,7 +24,10 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <asm/gpio.h>
+#include <asm/ppc4xx-gpio.h>
+
+/* Only compile this file for boards with GPIO support */
+#if defined(GPIO0_BASE)
 
 #if defined(CONFIG_SYS_4xx_GPIO_TABLE)
 gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
@@ -252,4 +255,6 @@ void gpio_set_chip_configuration(void)
 		}
 	}
 }
+
+#endif /* GPIO0_BASE */
 #endif /* CONFIG_SYS_4xx_GPIO_TABLE */
diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c
index c89bf37..c2d4973 100644
--- a/arch/powerpc/cpu/ppc4xx/interrupts.c
+++ b/arch/powerpc/cpu/ppc4xx/interrupts.c
@@ -36,7 +36,7 @@
 #include <command.h>
 #include <asm/processor.h>
 #include <asm/interrupt.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <ppc_asm.tmpl>
 #include <commproc.h>
 
diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S
index 4227a4c..417ba62 100644
--- a/arch/powerpc/cpu/ppc4xx/kgdb.S
+++ b/arch/powerpc/cpu/ppc4xx/kgdb.S
@@ -22,7 +22,7 @@
 
 #include <config.h>
 #include <command.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <version.h>
 
 #define CONFIG_405GP 1		/* needed for Linux kernel header files */
diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c
index 4fec126..3b28122 100644
--- a/arch/powerpc/cpu/ppc4xx/miiphy.c
+++ b/arch/powerpc/cpu/ppc4xx/miiphy.c
@@ -41,8 +41,8 @@
 #include <asm/io.h>
 #include <ppc_asm.tmpl>
 #include <commproc.h>
-#include <ppc4xx_enet.h>
-#include <405_mal.h>
+#include <asm/ppc4xx-emac.h>
+#include <asm/ppc4xx-mal.h>
 #include <miiphy.h>
 
 #if !defined(CONFIG_PHY_CLK_FREQ)
diff --git a/arch/powerpc/cpu/ppc4xx/reginfo.c b/arch/powerpc/cpu/ppc4xx/reginfo.c
index a975667..2f1ab9e 100644
--- a/arch/powerpc/cpu/ppc4xx/reginfo.c
+++ b/arch/powerpc/cpu/ppc4xx/reginfo.c
@@ -28,7 +28,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/ppc4xx-uic.h>
-#include <ppc4xx_enet.h>
+#include <asm/ppc4xx-emac.h>
 
 enum REGISTER_TYPE {
 	IDCR1,	/* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */
@@ -108,9 +108,9 @@ const struct cpu_register ppc4xx_reg[] = {
 	{"SDR0_SDSTP3",		IDCR6,	SDR0_SDSTP3},
 	{"SDR0_CUST0",		IDCR6,	SDR0_CUST0},
 	{"SDR0_CUST1",		IDCR6,	SDR0_CUST1},
-	{"SDR0_EBC0",		IDCR6,	SDR0_EBC0},
-	{"SDR0_AMP0",		IDCR6,	SD0_AMP0},
-	{"SDR0_AMP1",		IDCR6,	SD0_AMP1},
+	{"SDR0_EBC",		IDCR6,	SDR0_EBC},
+	{"SDR0_AMP0",		IDCR6,	SDR0_AMP0},
+	{"SDR0_AMP1",		IDCR6,	SDR0_AMP1},
 	{"SDR0_CP440",		IDCR6,	SDR0_CP440},
 	{"SDR0_CRYP0",		IDCR6,	SDR0_CRYP0},
 	{"SDR0_DDRCFG",		IDCR6,	SDR0_DDRCFG},
diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c
index 30c6e0e..b827daf 100644
--- a/arch/powerpc/cpu/ppc4xx/sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/sdram.c
@@ -28,7 +28,7 @@
  */
 
 #include <common.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <asm/processor.h>
 #include "sdram.h"
 #include "ecc.h"
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 906face..abd4e91 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 #include <ppc_asm.tmpl>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -902,7 +902,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
 	/*
 	 * Read CPR_PRIMAD register
 	 */
-	mfcpr(CPC0_PRIMAD, cpr_primad);
+	mfcpr(CPR0_PRIMAD, cpr_primad);
 
 	/*
 	 * Determine PLB_DIV.
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 4bad32f..7a65d9f 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -64,7 +64,7 @@
  *  address and (s)dram will be positioned at address 0
  */
 #include <config.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <timestamp.h>
 #include <version.h>
 
@@ -340,6 +340,9 @@ _start_440:
 	mfspr	r1,SPRN_DBCR0
 	andis.	r1, r1, 0x8000	/* test DBCR0[EDM] bit			*/
 	bne	skip_debug_init	/* if set, don't clear debug register	*/
+	mfspr	r1,SPRN_CCR0
+	ori	r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
+	mtspr	SPRN_CCR0,r1
 	mtspr	SPRN_DBCR0,r0
 	mtspr	SPRN_DBCR1,r0
 	mtspr	SPRN_DBCR2,r0
diff --git a/arch/powerpc/cpu/ppc4xx/tlb.c b/arch/powerpc/cpu/ppc4xx/tlb.c
index 24a9a9c..684da92 100644
--- a/arch/powerpc/cpu/ppc4xx/tlb.c
+++ b/arch/powerpc/cpu/ppc4xx/tlb.c
@@ -25,7 +25,7 @@
 
 #if defined(CONFIG_440)
 
-#include <ppc440.h>
+#include <asm/ppc440.h>
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
diff --git a/arch/powerpc/cpu/ppc4xx/uic.c b/arch/powerpc/cpu/ppc4xx/uic.c
index 8b1b259..324f0e9 100644
--- a/arch/powerpc/cpu/ppc4xx/uic.c
+++ b/arch/powerpc/cpu/ppc4xx/uic.c
@@ -36,7 +36,7 @@
 #include <command.h>
 #include <asm/processor.h>
 #include <asm/interrupt.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <ppc_asm.tmpl>
 #include <commproc.h>
 
diff --git a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c
index 7108777..eaa3de2 100644
--- a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c
+++ b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c
@@ -21,7 +21,7 @@
 #include <command.h>
 #include <asm/processor.h>
 #include <asm/interrupt.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <ppc_asm.tmpl>
 #include <commproc.h>
 #include <asm/io.h>
diff --git a/arch/powerpc/include/asm/4xx_pcie.h b/arch/powerpc/include/asm/4xx_pcie.h
index a0e88de..90e0bd9 100644
--- a/arch/powerpc/include/asm/4xx_pcie.h
+++ b/arch/powerpc/include/asm/4xx_pcie.h
@@ -11,7 +11,7 @@
 #ifndef __4XX_PCIE_H
 #define __4XX_PCIE_H
 
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <pci.h>
 
 #define DCRN_SDR0_CFGADDR	0x00e
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index c854ce9..2a323e1 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2010
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -176,18 +176,20 @@ typedef	struct	global_data {
 	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
 #endif
 	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
 } gd_t;
 
 /*
  * Global Data Flags
  */
-#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
-#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
-#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
-#define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
-#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
-#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
-#define GD_FLG_DISABLE_CONSOLE	0x00040		/* Disable console (in & out)	 */
+#define	GD_FLG_RELOC		0x00001	/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT		0x00002	/* Devices have been initialized	*/
+#define	GD_FLG_SILENT		0x00004	/* Silent mode				*/
+#define	GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed		*/
+#define	GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted		*/
+#define	GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized	*/
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)		*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
 
 #if 1
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r2")
diff --git a/arch/powerpc/include/asm/ppc405.h b/arch/powerpc/include/asm/ppc405.h
new file mode 100644
index 0000000..14a7a37
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc405.h
@@ -0,0 +1,80 @@
+/*----------------------------------------------------------------------------+
+|   This source code is dual-licensed.  You may use it under the terms of the
+|   GNU General Public License version 2, or under the license below.
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+#ifndef	__PPC405_H__
+#define __PPC405_H__
+
+/* Define bits and masks for real-mode storage attribute control registers */
+#define PPC_128MB_SACR_BIT(addr)	((addr) >> 27)
+#define PPC_128MB_SACR_VALUE(addr)	PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
+
+#ifndef CONFIG_IOP480
+#define CONFIG_SYS_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs */
+#else
+#define CONFIG_SYS_DCACHE_SIZE		(2 << 10)	/* For PLX IOP480(403)*/
+#endif
+
+/* DCR registers */
+#define PLB0_ACR	0x0087
+
+/* SDR registers */
+#define SDR0_PINSTP	0x0040
+
+/* CPR registers */
+#define CPR0_CLKUPD	0x0020
+#define CPR0_PLLC	0x0040
+#define CPR0_PLLD	0x0060
+#define CPR0_CPUD	0x0080
+#define CPR0_PLBD	0x00a0
+#define CPR0_OPBD0	0x00c0
+#define CPR0_PERD	0x00e0
+
+/*
+ * DMA
+ */
+#define DMA_DCR_BASE	0x0100
+#define DMACR0		(DMA_DCR_BASE + 0x00)  /* DMA channel control reg 0	*/
+#define DMACT0		(DMA_DCR_BASE + 0x01)  /* DMA count reg 0		*/
+#define DMADA0		(DMA_DCR_BASE + 0x02)  /* DMA destination address reg 0 */
+#define DMASA0		(DMA_DCR_BASE + 0x03)  /* DMA source address reg 0	*/
+#define DMASB0		(DMA_DCR_BASE + 0x04)  /* DMA sg descriptor addr 0	*/
+#define DMACR1		(DMA_DCR_BASE + 0x08)  /* DMA channel control reg 1	*/
+#define DMACT1		(DMA_DCR_BASE + 0x09)  /* DMA count reg 1		*/
+#define DMADA1		(DMA_DCR_BASE + 0x0a)  /* DMA destination address reg 1 */
+#define DMASA1		(DMA_DCR_BASE + 0x0b)  /* DMA source address reg 1	*/
+#define DMASB1		(DMA_DCR_BASE + 0x0c)  /* DMA sg descriptor addr 1	*/
+#define DMACR2		(DMA_DCR_BASE + 0x10)  /* DMA channel control reg 2	*/
+#define DMACT2		(DMA_DCR_BASE + 0x11)  /* DMA count reg 2		*/
+#define DMADA2		(DMA_DCR_BASE + 0x12)  /* DMA destination address reg 2 */
+#define DMASA2		(DMA_DCR_BASE + 0x13)  /* DMA source address reg 2	*/
+#define DMASB2		(DMA_DCR_BASE + 0x14)  /* DMA sg descriptor addr 2	*/
+#define DMACR3		(DMA_DCR_BASE + 0x18)  /* DMA channel control reg 3	*/
+#define DMACT3		(DMA_DCR_BASE + 0x19)  /* DMA count reg 3		*/
+#define DMADA3		(DMA_DCR_BASE + 0x1a)  /* DMA destination address reg 3 */
+#define DMASA3		(DMA_DCR_BASE + 0x1b)  /* DMA source address reg 3	*/
+#define DMASB3		(DMA_DCR_BASE + 0x1c)  /* DMA sg descriptor addr 3	*/
+#define DMASR		(DMA_DCR_BASE + 0x20)  /* DMA status reg		*/
+#define DMASGC		(DMA_DCR_BASE + 0x23)  /* DMA scatter/gather command reg*/
+#define DMAADR		(DMA_DCR_BASE + 0x24)  /* DMA address decode reg	*/
+
+#endif	/* __PPC405_H__ */
diff --git a/arch/powerpc/include/asm/ppc405cr.h b/arch/powerpc/include/asm/ppc405cr.h
new file mode 100644
index 0000000..01078f7
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc405cr.h
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC405CR_H_
+#define _PPC405CR_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM	/* IBM SDRAM controller */
+
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+/* DCR's */
+#define DCP0_CFGADDR	0x0014		/* Decompression controller addr reg */
+#define DCP0_CFGDATA	0x0015		/* Decompression controller data reg */
+#define OCM0_ISCNTL	0x0019	/* OCM I-side control reg */
+#define OCM0_DSARC	0x001a	/* OCM D-side address compare */
+#define OCM0_DSCNTL	0x001b	/* OCM D-side control */
+#define CPC0_PLLMR	0x00b0		/* PLL mode  register */
+#define CPC0_CR0	0x00b1		/* chip control register 0 */
+#define CPC0_CR1	0x00b2		/* chip control register 1 */
+#define CPC0_PSR	0x00b4		/* chip pin strapping reg */
+#define CPC0_EIRR	0x00b6		/* ext interrupt routing reg */
+#define CPC0_SR		0x00b8		/* Power management status */
+#define CPC0_ER		0x00b9		/* Power management enable */
+#define CPC0_FR		0x00ba		/* Power management force */
+#define CPC0_ECR	0x00aa		/* edge conditioner register */
+
+#define PLLMR_FWD_DIV_MASK	0xE0000000	/* Forward Divisor */
+#define PLLMR_FWD_DIV_BYPASS	0xE0000000
+#define PLLMR_FWD_DIV_3		0xA0000000
+#define PLLMR_FWD_DIV_4		0x80000000
+#define PLLMR_FWD_DIV_6		0x40000000
+
+#define PLLMR_FB_DIV_MASK	0x1E000000	/* Feedback Divisor */
+#define PLLMR_FB_DIV_1		0x02000000
+#define PLLMR_FB_DIV_2		0x04000000
+#define PLLMR_FB_DIV_3		0x06000000
+#define PLLMR_FB_DIV_4		0x08000000
+
+#define PLLMR_TUNING_MASK	0x01F80000
+
+#define PLLMR_CPU_TO_PLB_MASK	0x00060000	/* CPU:PLB Frequency Divisor */
+#define PLLMR_CPU_PLB_DIV_1	0x00000000
+#define PLLMR_CPU_PLB_DIV_2	0x00020000
+#define PLLMR_CPU_PLB_DIV_3	0x00040000
+#define PLLMR_CPU_PLB_DIV_4	0x00060000
+
+#define PLLMR_OPB_TO_PLB_MASK	0x00018000	/* OPB:PLB Frequency Divisor */
+#define PLLMR_OPB_PLB_DIV_1	0x00000000
+#define PLLMR_OPB_PLB_DIV_2	0x00008000
+#define PLLMR_OPB_PLB_DIV_3	0x00010000
+#define PLLMR_OPB_PLB_DIV_4	0x00018000
+
+#define PLLMR_PCI_TO_PLB_MASK	0x00006000	/* PCI:PLB Frequency Divisor */
+#define PLLMR_PCI_PLB_DIV_1	0x00000000
+#define PLLMR_PCI_PLB_DIV_2	0x00002000
+#define PLLMR_PCI_PLB_DIV_3	0x00004000
+#define PLLMR_PCI_PLB_DIV_4	0x00006000
+
+#define PLLMR_EXB_TO_PLB_MASK	0x00001800	/* External Bus:PLB Divisor */
+#define PLLMR_EXB_PLB_DIV_2	0x00000000
+#define PLLMR_EXB_PLB_DIV_3	0x00000800
+#define PLLMR_EXB_PLB_DIV_4	0x00001000
+#define PLLMR_EXB_PLB_DIV_5	0x00001800
+
+/* definitions for PPC405GPr (new mode strapping) */
+#define PLLMR_FWDB_DIV_MASK	0x00000007	/* Forward Divisor B */
+
+#define PSR_PLL_FWD_MASK	0xC0000000
+#define PSR_PLL_FDBACK_MASK	0x30000000
+#define PSR_PLL_TUNING_MASK	0x0E000000
+#define PSR_PLB_CPU_MASK	0x01800000
+#define PSR_OPB_PLB_MASK	0x00600000
+#define PSR_PCI_PLB_MASK	0x00180000
+#define PSR_EB_PLB_MASK		0x00060000
+#define PSR_ROM_WIDTH_MASK	0x00018000
+#define PSR_ROM_LOC		0x00004000
+#define PSR_PCI_ASYNC_EN	0x00001000
+#define PSR_PERCLK_SYNC_MODE_EN 0x00000800	/* PPC405GPr only */
+#define PSR_PCI_ARBIT_EN	0x00000400
+#define PSR_NEW_MODE_EN		0x00000020	/* PPC405GPr only */
+
+#endif /* _PPC405CR_H_ */
diff --git a/arch/powerpc/include/asm/ppc405ep.h b/arch/powerpc/include/asm/ppc405ep.h
new file mode 100644
index 0000000..9691604
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc405ep.h
@@ -0,0 +1,252 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC405EP_H_
+#define _PPC405EP_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM	/* IBM SDRAM controller */
+
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+/* DCR */
+#define OCM0_ISCNTL	0x0019	/* OCM I-side control reg */
+#define OCM0_DSARC	0x001a	/* OCM D-side address compare */
+#define OCM0_DSCNTL	0x001b	/* OCM D-side control */
+#define CPC0_PLLMR0	0x00f0	/* PLL mode  register 0	*/
+#define CPC0_BOOT	0x00f1	/* Clock status register	*/
+#define CPC0_CR1	0x00f2	/* Chip Control 1 register */
+#define CPC0_EPCTL	0x00f3	/* EMAC to PHY control register */
+#define CPC0_PLLMR1	0x00f4	/* PLL mode  register 1	*/
+#define CPC0_UCR	0x00f5	/* UART control register	*/
+#define CPC0_SRR	0x00f6	/* Soft Reset register */
+#define CPC0_PCI	0x00f9	/* PCI control register	*/
+
+/* Defines for CPC0_EPCTL register */
+#define CPC0_EPCTL_E0NFE	0x80000000
+#define CPC0_EPCTL_E1NFE	0x40000000
+
+/* Defines for CPC0_PCI Register */
+#define CPC0_PCI_SPE		0x00000010	/* PCIINT/WE select	 */
+#define CPC0_PCI_HOST_CFG_EN	0x00000008	/* PCI host config Enable */
+#define CPC0_PCI_ARBIT_EN	0x00000001	/* PCI Internal Arb Enabled */
+
+/* Defines for CPC0_BOOR Register */
+#define CPC0_BOOT_SEP		0x00000002	/* serial EEPROM present */
+
+/* Bit definitions */
+#define PLLMR0_CPU_DIV_MASK	0x00300000	/* CPU clock divider */
+#define PLLMR0_CPU_DIV_BYPASS	0x00000000
+#define PLLMR0_CPU_DIV_2	0x00100000
+#define PLLMR0_CPU_DIV_3	0x00200000
+#define PLLMR0_CPU_DIV_4	0x00300000
+
+#define PLLMR0_CPU_TO_PLB_MASK	0x00030000	/* CPU:PLB Frequency Divisor */
+#define PLLMR0_CPU_PLB_DIV_1	0x00000000
+#define PLLMR0_CPU_PLB_DIV_2	0x00010000
+#define PLLMR0_CPU_PLB_DIV_3	0x00020000
+#define PLLMR0_CPU_PLB_DIV_4	0x00030000
+
+#define PLLMR0_OPB_TO_PLB_MASK	0x00003000	/* OPB:PLB Frequency Divisor */
+#define PLLMR0_OPB_PLB_DIV_1	0x00000000
+#define PLLMR0_OPB_PLB_DIV_2	0x00001000
+#define PLLMR0_OPB_PLB_DIV_3	0x00002000
+#define PLLMR0_OPB_PLB_DIV_4	0x00003000
+
+#define PLLMR0_EXB_TO_PLB_MASK	0x00000300	/* External Bus:PLB Divisor */
+#define PLLMR0_EXB_PLB_DIV_2	0x00000000
+#define PLLMR0_EXB_PLB_DIV_3	0x00000100
+#define PLLMR0_EXB_PLB_DIV_4	0x00000200
+#define PLLMR0_EXB_PLB_DIV_5	0x00000300
+
+#define PLLMR0_MAL_TO_PLB_MASK	0x00000030	/* MAL:PLB Divisor */
+#define PLLMR0_MAL_PLB_DIV_1	0x00000000
+#define PLLMR0_MAL_PLB_DIV_2	0x00000010
+#define PLLMR0_MAL_PLB_DIV_3	0x00000020
+#define PLLMR0_MAL_PLB_DIV_4	0x00000030
+
+#define PLLMR0_PCI_TO_PLB_MASK	0x00000003	/* PCI:PLB Frequency Divisor */
+#define PLLMR0_PCI_PLB_DIV_1	0x00000000
+#define PLLMR0_PCI_PLB_DIV_2	0x00000001
+#define PLLMR0_PCI_PLB_DIV_3	0x00000002
+#define PLLMR0_PCI_PLB_DIV_4	0x00000003
+
+#define PLLMR1_SSCS_MASK	0x80000000	/* Select system clock source */
+#define PLLMR1_PLLR_MASK	0x40000000	/* PLL reset */
+#define PLLMR1_FBMUL_MASK	0x00F00000	/* PLL feedback multiplier value */
+
+#define PLLMR1_FWDVA_MASK	0x00070000	/* PLL forward divider A value */
+#define PLLMR1_FWDVB_MASK	0x00007000	/* PLL forward divider B value */
+#define PLLMR1_TUNING_MASK	0x000003FF	/* PLL tune bits */
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE		0x80000000
+#define CPC0_PLLMR1_SSCS	0x80000000
+#define PLL_RESET		0x40000000
+#define CPC0_PLLMR1_PLLR	0x40000000
+/* Feedback multiplier */
+#define PLL_FBKDIV		0x00F00000
+#define CPC0_PLLMR1_FBDV	0x00F00000
+#define PLL_FBKDIV_16		0x00000000
+#define PLL_FBKDIV_1		0x00100000
+#define PLL_FBKDIV_2		0x00200000
+#define PLL_FBKDIV_3		0x00300000
+#define PLL_FBKDIV_4		0x00400000
+#define PLL_FBKDIV_5		0x00500000
+#define PLL_FBKDIV_6		0x00600000
+#define PLL_FBKDIV_7		0x00700000
+#define PLL_FBKDIV_8		0x00800000
+#define PLL_FBKDIV_9		0x00900000
+#define PLL_FBKDIV_10		0x00A00000
+#define PLL_FBKDIV_11		0x00B00000
+#define PLL_FBKDIV_12		0x00C00000
+#define PLL_FBKDIV_13		0x00D00000
+#define PLL_FBKDIV_14		0x00E00000
+#define PLL_FBKDIV_15		0x00F00000
+/* Forward A divisor */
+#define PLL_FWDDIVA		0x00070000
+#define CPC0_PLLMR1_FWDVA	0x00070000
+#define PLL_FWDDIVA_8		0x00000000
+#define PLL_FWDDIVA_7		0x00010000
+#define PLL_FWDDIVA_6		0x00020000
+#define PLL_FWDDIVA_5		0x00030000
+#define PLL_FWDDIVA_4		0x00040000
+#define PLL_FWDDIVA_3		0x00050000
+#define PLL_FWDDIVA_2		0x00060000
+#define PLL_FWDDIVA_1		0x00070000
+/* Forward B divisor */
+#define PLL_FWDDIVB		0x00007000
+#define CPC0_PLLMR1_FWDVB	0x00007000
+#define PLL_FWDDIVB_8		0x00000000
+#define PLL_FWDDIVB_7		0x00001000
+#define PLL_FWDDIVB_6		0x00002000
+#define PLL_FWDDIVB_5		0x00003000
+#define PLL_FWDDIVB_4		0x00004000
+#define PLL_FWDDIVB_3		0x00005000
+#define PLL_FWDDIVB_2		0x00006000
+#define PLL_FWDDIVB_1		0x00007000
+/* PLL tune bits */
+#define PLL_TUNE_MASK		0x000003FF
+#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3 */
+#define PLL_TUNE_4_M_6		0x00000134	/*  3 <  M <= 6 */
+#define PLL_TUNE_7_M_10		0x00000138	/*  6 <  M <= 10 */
+#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <  M <= 14 */
+#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <  M <= 40 */
+#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz */
+#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz */
+
+/* Defines for CPC0_PLLMR0 Register fields */
+/* CPU divisor */
+#define PLL_CPUDIV		0x00300000
+#define CPC0_PLLMR0_CCDV	0x00300000
+#define PLL_CPUDIV_1		0x00000000
+#define PLL_CPUDIV_2		0x00100000
+#define PLL_CPUDIV_3		0x00200000
+#define PLL_CPUDIV_4		0x00300000
+/* PLB divisor */
+#define PLL_PLBDIV		0x00030000
+#define CPC0_PLLMR0_CBDV	0x00030000
+#define PLL_PLBDIV_1		0x00000000
+#define PLL_PLBDIV_2		0x00010000
+#define PLL_PLBDIV_3		0x00020000
+#define PLL_PLBDIV_4		0x00030000
+/* OPB divisor */
+#define PLL_OPBDIV		0x00003000
+#define CPC0_PLLMR0_OPDV	0x00003000
+#define PLL_OPBDIV_1		0x00000000
+#define PLL_OPBDIV_2		0x00001000
+#define PLL_OPBDIV_3		0x00002000
+#define PLL_OPBDIV_4		0x00003000
+/* EBC divisor */
+#define PLL_EXTBUSDIV		0x00000300
+#define CPC0_PLLMR0_EPDV	0x00000300
+#define PLL_EXTBUSDIV_2		0x00000000
+#define PLL_EXTBUSDIV_3		0x00000100
+#define PLL_EXTBUSDIV_4		0x00000200
+#define PLL_EXTBUSDIV_5		0x00000300
+/* MAL divisor */
+#define PLL_MALDIV		0x00000030
+#define CPC0_PLLMR0_MPDV	0x00000030
+#define PLL_MALDIV_1		0x00000000
+#define PLL_MALDIV_2		0x00000010
+#define PLL_MALDIV_3		0x00000020
+#define PLL_MALDIV_4		0x00000030
+/* PCI divisor */
+#define PLL_PCIDIV		0x00000003
+#define CPC0_PLLMR0_PPFD	0x00000003
+#define PLL_PCIDIV_1		0x00000000
+#define PLL_PCIDIV_2		0x00000001
+#define PLL_PCIDIV_3		0x00000002
+#define PLL_PCIDIV_4		0x00000003
+
+/*
+ * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+ * assuming a 33.3MHz input clock to the 405EP.
+ */
+#define PLLMR0_266_133_66	(PLL_CPUDIV_1 | PLL_PLBDIV_2 |     \
+				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+				 PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_66	(PLL_FBKDIV_8  |			\
+				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
+				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PLLMR0_133_66_66_33	(PLL_CPUDIV_1 | PLL_PLBDIV_1 |		\
+				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				 PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_133_66_66_33	(PLL_FBKDIV_4  |			\
+				 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |	\
+				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_200_100_50_33	(PLL_CPUDIV_1 | PLL_PLBDIV_2 |		\
+				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				 PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_200_100_50_33	(PLL_FBKDIV_6  |			\
+				 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |	\
+				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_133_66_33	(PLL_CPUDIV_1 | PLL_PLBDIV_2 |		\
+				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				 PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_66_33	(PLL_FBKDIV_8  |			\
+				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
+				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_66_33_33	(PLL_CPUDIV_1 | PLL_PLBDIV_4 |		\
+				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
+				 PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_266_66_33_33	(PLL_FBKDIV_8  |			\
+				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
+				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_333_111_55_37	(PLL_CPUDIV_1 | PLL_PLBDIV_3 |		\
+				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
+				 PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37	(PLL_FBKDIV_10  |			\
+				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
+				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#define PLLMR0_333_111_55_111	(PLL_CPUDIV_1 | PLL_PLBDIV_3 |		\
+				 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
+				 PLL_MALDIV_1 | PLL_PCIDIV_1)
+#define PLLMR1_333_111_55_111	(PLL_FBKDIV_10  |			\
+				 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |	\
+				 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#endif /* _PPC405EP_H_ */
diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h
new file mode 100644
index 0000000..36d3149
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc405ex.h
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC405EX_H_
+#define _PPC405EX_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
+
+#define CONFIG_NAND_NDFC
+
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
+
+/* SDR */
+#define SDR0_SDCS0		0x0060
+#define SDR0_UART0		0x0120	/* UART0 Config */
+#define SDR0_UART1		0x0121	/* UART1 Config */
+#define SDR0_SRST		0x0200
+#define SDR0_CUST0		0x4000
+#define SDR0_PFC0		0x4100
+#define SDR0_PFC1		0x4101
+#define SDR0_MFR		0x4300	/* SDR0_MFR reg */
+
+#define SDR0_SDCS_SDD		(0x80000000 >> 31)
+
+#define SDR0_SRST_DMC		(0x80000000 >> 10)
+
+#define SDR0_CUST0_MUX_E_N_G_MASK	0xC0000000 /* Mux_Emac_NDFC_GPIO */
+#define SDR0_CUST0_MUX_EMAC_SEL		0x40000000 /* Emac Selection */
+#define SDR0_CUST0_MUX_NDFC_SEL		0x80000000 /* NDFC Selection */
+#define SDR0_CUST0_MUX_GPIO_SEL		0xC0000000 /* GPIO Selection */
+
+#define SDR0_CUST0_NDFC_EN_MASK		0x20000000 /* NDFC Enable Mask */
+#define SDR0_CUST0_NDFC_ENABLE		0x20000000 /* NDFC Enable */
+#define SDR0_CUST0_NDFC_DISABLE		0x00000000 /* NDFC Disable */
+
+#define SDR0_CUST0_NDFC_BW_MASK	  	0x10000000 /* NDFC Boot Width */
+#define SDR0_CUST0_NDFC_BW_16_BIT 	0x10000000 /* NDFC Boot Width= 16 Bit */
+#define SDR0_CUST0_NDFC_BW_8_BIT  	0x00000000 /* NDFC Boot Width=  8 Bit */
+
+#define SDR0_CUST0_NDFC_BP_MASK		0x0F000000 /* NDFC Boot Page */
+#define SDR0_CUST0_NDFC_BP_ENCODE(n)	((((u32)(n)) & 0xF) << 24)
+#define SDR0_CUST0_NDFC_BP_DECODE(n)	((((u32)(n)) >> 24) & 0xF)
+
+#define SDR0_CUST0_NDFC_BAC_MASK	0x00C00000 /* NDFC Boot Address Cycle */
+#define SDR0_CUST0_NDFC_BAC_ENCODE(n)	((((u32)(n)) & 0x3) << 22)
+#define SDR0_CUST0_NDFC_BAC_DECODE(n)	((((u32)(n)) >> 22) & 0x3)
+
+#define SDR0_CUST0_NDFC_ARE_MASK	0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_ENABLE	0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_DISABLE	0x00000000 /* NDFC Auto Read Disable */
+
+#define SDR0_CUST0_NRB_MASK		0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY		0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY		0x00000000 /* Ready */
+
+#define SDR0_PFC1_U1ME			0x02000000
+#define SDR0_PFC1_U0ME			0x00080000
+#define SDR0_PFC1_U0IM			0x00040000
+#define SDR0_PFC1_SIS			0x00020000
+#define SDR0_PFC1_DMAAEN		0x00010000
+#define SDR0_PFC1_DMADEN		0x00008000
+#define SDR0_PFC1_USBEN			0x00004000
+#define SDR0_PFC1_AHBSWAP		0x00000020
+#define SDR0_PFC1_USBBIGEN		0x00000010
+#define SDR0_PFC1_GPT_FREQ		0x0000000f
+
+#endif /* _PPC405EX_H_ */
diff --git a/arch/powerpc/include/asm/ppc405ez.h b/arch/powerpc/include/asm/ppc405ez.h
new file mode 100644
index 0000000..cb8e994
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc405ez.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC405EZ_H_
+#define _PPC405EZ_H_
+
+#define CONFIG_NAND_NDFC
+
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+#define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
+
+/* DCR register */
+#define OCM0_PLBCR1	0x0020	/* OCM PLB3 Bank 1 Config */
+#define OCM0_PLBCR2	0x0021	/* OCM PLB3 Bank 2 Config */
+#define OCM0_PLBBEAR	0x0022	/* OCM PLB3 Bus Error Add */
+#define OCM0_DSRC1	0x0028	/* OCM D-side Bank 1 Config */
+#define OCM0_DSRC2	0x0029	/* OCM D-side Bank 2 Config */
+#define OCM0_ISRC1	0x002A	/* OCM I-side Bank 1Config */
+#define OCM0_ISRC2	0x002B	/* OCM I-side Bank 2 Config */
+#define OCM0_DISDPC	0x002C	/* OCM D-/I-side Data Par Chk */
+
+/* SDR register */
+#define SDR0_NAND0	0x4000
+#define SDR0_ULTRA0	0x4040
+#define SDR0_ULTRA1	0x4050
+#define SDR0_ICINTSTAT	0x4510
+
+/* CPR register */
+#define CPR0_PRIMAD	0x0080
+#define CPR0_PERD0	0x00e0
+#define CPR0_PERD1	0x00e1
+#define CPR0_PERC0	0x0180
+
+#define	MAL_DCR_BASE	0x380
+
+#define SDR_NAND0_NDEN		0x80000000
+#define SDR_NAND0_NDBTEN	0x40000000
+#define SDR_NAND0_NDBADR_MASK	0x30000000
+#define SDR_NAND0_NDBPG_MASK	0x0f000000
+#define SDR_NAND0_NDAREN	0x00800000
+#define SDR_NAND0_NDRBEN	0x00400000
+
+#define SDR_ULTRA0_NDGPIOBP	0x80000000
+#define SDR_ULTRA0_CSN_MASK	0x78000000
+#define SDR_ULTRA0_CSNSEL0	0x40000000
+#define SDR_ULTRA0_CSNSEL1	0x20000000
+#define SDR_ULTRA0_CSNSEL2	0x10000000
+#define SDR_ULTRA0_CSNSEL3	0x08000000
+#define SDR_ULTRA0_EBCRDYEN	0x04000000
+#define SDR_ULTRA0_SPISSINEN	0x02000000
+#define SDR_ULTRA0_NFSRSTEN	0x01000000
+
+#define SDR_ULTRA1_LEDNENABLE	0x40000000
+
+#define SDR_ICRX_STAT		0x80000000
+#define SDR_ICTX0_STAT		0x40000000
+#define SDR_ICTX1_STAT		0x20000000
+
+#define CPR_CLKUPD_ENPLLCH_EN	0x40000000 /* Enable CPR PLL Changes */
+#define CPR_CLKUPD_ENDVCH_EN	0x20000000 /* Enable CPR Sys. Div. Changes */
+#define CPR_PERD0_SPIDV_MASK	0x000F0000 /* SPI Clock Divider */
+
+#define PLLC_SRC_MASK		0x20000000 /* PLL feedback source */
+
+#define PLLD_FBDV_MASK		0x1F000000 /* PLL feedback divider value */
+#define PLLD_FWDVA_MASK		0x000F0000 /* PLL forward divider A value */
+#define PLLD_FWDVB_MASK		0x00000700 /* PLL forward divider B value */
+
+#define PRIMAD_CPUDV_MASK	0x0F000000 /* CPU Clock Divisor Mask */
+#define PRIMAD_PLBDV_MASK	0x000F0000 /* PLB Clock Divisor Mask */
+#define PRIMAD_OPBDV_MASK	0x00000F00 /* OPB Clock Divisor Mask */
+#define PRIMAD_EBCDV_MASK	0x0000000F /* EBC Clock Divisor Mask */
+
+#define PERD0_PWMDV_MASK	0xFF000000 /* PWM Divider Mask */
+#define PERD0_SPIDV_MASK	0x000F0000 /* SPI Divider Mask */
+#define PERD0_U0DV_MASK		0x0000FF00 /* UART 0 Divider Mask */
+#define PERD0_U1DV_MASK		0x000000FF /* UART 1 Divider Mask */
+
+#endif /* _PPC405EZ_H_ */
diff --git a/arch/powerpc/include/asm/ppc405gp.h b/arch/powerpc/include/asm/ppc405gp.h
new file mode 100644
index 0000000..91beeb8
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc405gp.h
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC405GP_H_
+#define _PPC405GP_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM	/* IBM SDRAM controller */
+
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+/* DCR's */
+#define DCP0_CFGADDR	0x0014		/* Decompression controller addr reg */
+#define DCP0_CFGDATA	0x0015		/* Decompression controller data reg */
+#define OCM0_ISCNTL	0x0019	/* OCM I-side control reg */
+#define OCM0_DSARC	0x001a	/* OCM D-side address compare */
+#define OCM0_DSCNTL	0x001b	/* OCM D-side control */
+#define CPC0_PLLMR	0x00b0		/* PLL mode  register */
+#define CPC0_CR0	0x00b1		/* chip control register 0 */
+#define CPC0_CR1	0x00b2		/* chip control register 1 */
+#define CPC0_PSR	0x00b4		/* chip pin strapping reg */
+#define CPC0_EIRR	0x00b6		/* ext interrupt routing reg */
+#define CPC0_SR		0x00b8		/* Power management status */
+#define CPC0_ER		0x00b9		/* Power management enable */
+#define CPC0_FR		0x00ba		/* Power management force */
+#define CPC0_ECR	0x00aa		/* edge conditioner register */
+
+/* values for kiar register - indirect addressing of these regs */
+#define KCONF		0x40		/* decompression core config register */
+
+#define PLLMR_FWD_DIV_MASK	0xE0000000	/* Forward Divisor */
+#define PLLMR_FWD_DIV_BYPASS	0xE0000000
+#define PLLMR_FWD_DIV_3		0xA0000000
+#define PLLMR_FWD_DIV_4		0x80000000
+#define PLLMR_FWD_DIV_6		0x40000000
+
+#define PLLMR_FB_DIV_MASK	0x1E000000	/* Feedback Divisor */
+#define PLLMR_FB_DIV_1		0x02000000
+#define PLLMR_FB_DIV_2		0x04000000
+#define PLLMR_FB_DIV_3		0x06000000
+#define PLLMR_FB_DIV_4		0x08000000
+
+#define PLLMR_TUNING_MASK	0x01F80000
+
+#define PLLMR_CPU_TO_PLB_MASK	0x00060000	/* CPU:PLB Frequency Divisor */
+#define PLLMR_CPU_PLB_DIV_1	0x00000000
+#define PLLMR_CPU_PLB_DIV_2	0x00020000
+#define PLLMR_CPU_PLB_DIV_3	0x00040000
+#define PLLMR_CPU_PLB_DIV_4	0x00060000
+
+#define PLLMR_OPB_TO_PLB_MASK	0x00018000	/* OPB:PLB Frequency Divisor */
+#define PLLMR_OPB_PLB_DIV_1	0x00000000
+#define PLLMR_OPB_PLB_DIV_2	0x00008000
+#define PLLMR_OPB_PLB_DIV_3	0x00010000
+#define PLLMR_OPB_PLB_DIV_4	0x00018000
+
+#define PLLMR_PCI_TO_PLB_MASK	0x00006000	/* PCI:PLB Frequency Divisor */
+#define PLLMR_PCI_PLB_DIV_1	0x00000000
+#define PLLMR_PCI_PLB_DIV_2	0x00002000
+#define PLLMR_PCI_PLB_DIV_3	0x00004000
+#define PLLMR_PCI_PLB_DIV_4	0x00006000
+
+#define PLLMR_EXB_TO_PLB_MASK	0x00001800	/* External Bus:PLB Divisor */
+#define PLLMR_EXB_PLB_DIV_2	0x00000000
+#define PLLMR_EXB_PLB_DIV_3	0x00000800
+#define PLLMR_EXB_PLB_DIV_4	0x00001000
+#define PLLMR_EXB_PLB_DIV_5	0x00001800
+
+/* definitions for PPC405GPr (new mode strapping) */
+#define PLLMR_FWDB_DIV_MASK	0x00000007	/* Forward Divisor B */
+
+#define PSR_PLL_FWD_MASK	0xC0000000
+#define PSR_PLL_FDBACK_MASK	0x30000000
+#define PSR_PLL_TUNING_MASK	0x0E000000
+#define PSR_PLB_CPU_MASK	0x01800000
+#define PSR_OPB_PLB_MASK	0x00600000
+#define PSR_PCI_PLB_MASK	0x00180000
+#define PSR_EB_PLB_MASK		0x00060000
+#define PSR_ROM_WIDTH_MASK	0x00018000
+#define PSR_ROM_LOC		0x00004000
+#define PSR_PCI_ASYNC_EN	0x00001000
+#define PSR_PERCLK_SYNC_MODE_EN 0x00000800	/* PPC405GPr only */
+#define PSR_PCI_ARBIT_EN	0x00000400
+#define PSR_NEW_MODE_EN		0x00000020	/* PPC405GPr only */
+
+#endif /* _PPC405GP_H_ */
diff --git a/arch/powerpc/include/asm/ppc440.h b/arch/powerpc/include/asm/ppc440.h
new file mode 100644
index 0000000..0da6618
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc440.h
@@ -0,0 +1,190 @@
+/*----------------------------------------------------------------------------+
+|   This source code is dual-licensed.  You may use it under the terms of the
+|   GNU General Public License version 2, or under the license below.
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PPC440_H__
+#define __PPC440_H__
+
+#define CONFIG_SYS_DCACHE_SIZE		(32 << 10)	/* For AMCC 440 CPUs */
+
+/*
+ * DCRs & Related
+ */
+
+/* Memory mapped registers */
+#define PCIL0_CFGADR	(CONFIG_SYS_PCI_BASE + 0x0ec00000)
+#define PCIL0_CFGDATA	(CONFIG_SYS_PCI_BASE + 0x0ec00004)
+#define PCIL0_CFGBASE	(CONFIG_SYS_PCI_BASE + 0x0ec80000)
+#define PCIL0_IOBASE	(CONFIG_SYS_PCI_BASE + 0x08000000)
+
+/* DCR registers */
+
+/* CPR register declarations */
+#define CPR0_PLLC	0x0040
+#define CPR0_PLLD	0x0060
+#define CPR0_PRIMAD0	0x0080
+#define CPR0_PRIMBD0	0x00a0
+#define CPR0_OPBD0	0x00c0
+#define CPR0_PERD	0x00e0
+#define CPR0_MALD	0x0100
+#define CPR0_SPCID	0x0120
+#define CPR0_ICFG	0x0140
+
+/* SDR register definations */
+#define SDR0_SDSTP0	0x0020
+#define SDR0_SDSTP1	0x0021
+#define SDR0_PINSTP	0x0040
+#define SDR0_SDCS0	0x0060
+#define SDR0_ECID0	0x0080
+#define SDR0_ECID1	0x0081
+#define SDR0_ECID2	0x0082
+#define SDR0_ECID3	0x0083
+#define SDR0_DDR0	0x00e1
+#define SDR0_EBC	0x0100
+#define SDR0_UART0	0x0120
+#define SDR0_UART1	0x0121
+#define SDR0_UART2	0x0122
+#define SDR0_UART3	0x0123
+#define SDR0_CP440	0x0180
+#define SDR0_XCR	0x01c0
+#define SDR0_XCR0	0x01c0
+#define SDR0_XPLLC	0x01c1
+#define SDR0_XPLLD	0x01c2
+#define SDR0_SRST	0x0200
+#define SDR0_SRST0	SDR0_SRST
+#define SDR0_SRST1	0x0201
+#define SDR0_AMP0	0x0240
+#define SDR0_AMP1	0x0241
+#define SDR0_USB0	0x0320
+#define SDR0_CUST0	0x4000
+#define SDR0_CUST1	0x4002
+#define SDR0_CUST2	0x4004
+#define SDR0_CUST3	0x4006
+#define SDR0_PFC0	0x4100
+#define SDR0_PFC1	0x4101
+#define SDR0_PFC2   	0x4102
+#define SDR0_PFC4	0x4104
+#define SDR0_MFR	0x4300
+
+#define SDR0_DDR0_DDRM_DECODE(n)	((((u32)(n)) >> 29) & 0x03)
+
+#define SDR0_PCI0_PAE_MASK		(0x80000000 >> 0)
+#define SDR0_XCR0_PAE_MASK		(0x80000000 >> 0)
+
+#define SDR0_PFC0_GEIE_MASK		0x00003e00
+#define SDR0_PFC0_GEIE_TRE		0x00003e00
+#define SDR0_PFC0_GEIE_NOTRE		0x00000000
+#define SDR0_PFC0_TRE_MASK		(0x80000000 >> 23)
+#define SDR0_PFC0_TRE_DISABLE		0x00000000
+#define SDR0_PFC0_TRE_ENABLE		(0x80000000 >> 23)
+
+/*
+ * Core Configuration/MMU configuration for 440
+ */
+#define CCR0_DAPUIB		0x00100000
+#define CCR0_DTB		0x00008000
+
+#define SDR0_SDCS_SDD		(0x80000000 >> 31)
+
+/* todo: move this code from macro offsets to struct */
+#define PCIL0_VENDID		(PCIL0_CFGBASE + PCI_VENDOR_ID )
+#define PCIL0_DEVID		(PCIL0_CFGBASE + PCI_DEVICE_ID )
+#define PCIL0_CMD		(PCIL0_CFGBASE + PCI_COMMAND )
+#define PCIL0_STATUS		(PCIL0_CFGBASE + PCI_STATUS )
+#define PCIL0_REVID		(PCIL0_CFGBASE + PCI_REVISION_ID )
+#define PCIL0_CLS		(PCIL0_CFGBASE + PCI_CLASS_CODE)
+#define PCIL0_CACHELS		(PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
+#define PCIL0_LATTIM		(PCIL0_CFGBASE + PCI_LATENCY_TIMER )
+#define PCIL0_HDTYPE		(PCIL0_CFGBASE + PCI_HEADER_TYPE )
+#define PCIL0_BIST		(PCIL0_CFGBASE + PCI_BIST )
+#define PCIL0_BAR0		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
+#define PCIL0_BAR1		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
+#define PCIL0_BAR2		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
+#define PCIL0_BAR3		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
+#define PCIL0_BAR4		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
+#define PCIL0_BAR5		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
+#define PCIL0_CISPTR		(PCIL0_CFGBASE + PCI_CARDBUS_CIS )
+#define PCIL0_SBSYSVID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
+#define PCIL0_SBSYSID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
+#define PCIL0_EROMBA		(PCIL0_CFGBASE + PCI_ROM_ADDRESS )
+#define PCIL0_CAP		(PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
+#define PCIL0_RES0		(PCIL0_CFGBASE + 0x0035 )
+#define PCIL0_RES1		(PCIL0_CFGBASE + 0x0036 )
+#define PCIL0_RES2		(PCIL0_CFGBASE + 0x0038 )
+#define PCIL0_INTLN		(PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
+#define PCIL0_INTPN		(PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
+
+#define PCIL0_MINGNT		(PCIL0_CFGBASE + PCI_MIN_GNT )
+#define PCIL0_MAXLTNCY		(PCIL0_CFGBASE + PCI_MAX_LAT )
+
+#define PCIL0_POM0LAL		(PCIL0_CFGBASE + 0x0068)
+#define PCIL0_POM0LAH		(PCIL0_CFGBASE + 0x006c)
+#define PCIL0_POM0SA		(PCIL0_CFGBASE + 0x0070)
+#define PCIL0_POM0PCIAL		(PCIL0_CFGBASE + 0x0074)
+#define PCIL0_POM0PCIAH		(PCIL0_CFGBASE + 0x0078)
+#define PCIL0_POM1LAL		(PCIL0_CFGBASE + 0x007c)
+#define PCIL0_POM1LAH		(PCIL0_CFGBASE + 0x0080)
+#define PCIL0_POM1SA		(PCIL0_CFGBASE + 0x0084)
+#define PCIL0_POM1PCIAL		(PCIL0_CFGBASE + 0x0088)
+#define PCIL0_POM1PCIAH		(PCIL0_CFGBASE + 0x008c)
+#define PCIL0_POM2SA		(PCIL0_CFGBASE + 0x0090)
+
+#define PCIL0_PIM0SA		(PCIL0_CFGBASE + 0x0098)
+#define PCIL0_PIM0LAL		(PCIL0_CFGBASE + 0x009c)
+#define PCIL0_PIM0LAH		(PCIL0_CFGBASE + 0x00a0)
+#define PCIL0_PIM1SA		(PCIL0_CFGBASE + 0x00a4)
+#define PCIL0_PIM1LAL		(PCIL0_CFGBASE + 0x00a8)
+#define PCIL0_PIM1LAH		(PCIL0_CFGBASE + 0x00ac)
+#define PCIL0_PIM2SA		(PCIL0_CFGBASE + 0x00b0)
+#define PCIL0_PIM2LAL		(PCIL0_CFGBASE + 0x00b4)
+#define PCIL0_PIM2LAH		(PCIL0_CFGBASE + 0x00b8)
+
+#define PCIL0_STS		(PCIL0_CFGBASE + 0x00e0)
+
+#endif	/* __PPC440_H__ */
diff --git a/arch/powerpc/include/asm/ppc440ep_gr.h b/arch/powerpc/include/asm/ppc440ep_gr.h
new file mode 100644
index 0000000..dfd1532
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc440ep_gr.h
@@ -0,0 +1,244 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC440EP_GR_H_
+#define _PPC440EP_GR_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR	/* IBM DDR controller */
+
+#define CONFIG_NAND_NDFC
+
+/*
+ * Some SoC specific registers (not common for all 440 SoC's)
+ */
+
+/* Memory mapped registers */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
+#define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
+
+/* SDR's */
+#define SDR0_PCI0	0x0300
+#define SDR0_SDSTP2	0x4001
+#define SDR0_SDSTP3	0x4003
+
+#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 21)
+#define SDR0_SDSTP1_PAME_MASK		(0x80000000 >> 27)
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1_U1ME_MASK		0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR		0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS		0x02000000 /* UART1 in CTS/RTS Mode */
+#define SDR0_PFC1_U0ME_MASK		0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR		0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS		0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK		0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS		0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS		0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK		0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL		0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL		0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK		0x00010000 /* USB2D_RX_Active / EBC_Hold
+						      Req Selection */
+#define SDR0_PFC1_UES_USB2D_SEL		0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL		0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK		0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
+						      Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL		0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL	0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK		0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
+						      Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL		0x00000000 /* EBC Mast.Ext.Req.En.
+						      Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL	0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK		0x00002000 /* USB2 Device Packet Reject
+						      Selection */
+#define SDR0_PFC1_UPR_DISABLE		0x00000000 /* USB2 Device Packet Reject
+						      Disable */
+#define SDR0_PFC1_UPR_ENABLE		0x00002000 /* USB2 Device Packet Reject
+						      Enable */
+#define SDR0_PFC1_PLB_PME_MASK		0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
+						      Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL	0x00000000 /* PLB3 Performance Monitor
+						      Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL	0x00001000 /* PLB3 Performance Monitor
+						      Enable */
+#define SDR0_PFC1_GFGGI_MASK		0x0000000F /* GPT Frequency Generation
+						      Gated In */
+
+/* USB Control Register */
+#define SDR0_USB0_USB_DEVSEL_MASK	0x00000002 /* USB Device Selection */
+#define SDR0_USB0_USB20D_DEVSEL		0x00000000 /* USB2.0 Device Selected */
+#define SDR0_USB0_USB11D_DEVSEL		0x00000002 /* USB1.1 Device Selected */
+#define SDR0_USB0_LEEN_MASK		0x00000001 /* Little Endian selection */
+#define SDR0_USB0_LEEN_DISABLE		0x00000000 /* Little Endian Disable */
+#define SDR0_USB0_LEEN_ENABLE		0x00000001 /* Little Endian Enable */
+
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR_ETH0_CLK_SEL_MASK	0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH0_CLK_SEL_EXT	0x00000000
+#define SDR0_MFR_ETH1_CLK_SEL_MASK	0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL_EXT	0x00000000
+#define SDR0_MFR_ZMII_MODE_MASK		0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII		0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII		0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_RMII_10M	0x02000000 /* ZMII Mode RMII - 10 Mbs */
+#define SDR0_MFR_ZMII_MODE_RMII_100M	0x03000000 /* ZMII Mode RMII - 100 Mbs */
+#define SDR0_MFR_ZMII_MODE_BIT0		0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1		0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ZM_ENCODE(n)		((((u32)(n)) & 0x3) << 24)
+#define SDR0_MFR_ZM_DECODE(n)		((((u32)(n)) << 24) & 0x3)
+
+#define SDR0_MFR_ERRATA3_EN0		0x00800000
+#define SDR0_MFR_ERRATA3_EN1		0x00400000
+#define SDR0_MFR_PKT_REJ_MASK		0x00180000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN		0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0		0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1		0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL		0x00200000 /* Packet Reject Polarity */
+
+/* CUST0 Customer Configuration Register0 */
+#define SDR0_CUST0_MUX_E_N_G_MASK	0xC0000000 /* Mux_Emac_NDFC_GPIO */
+#define SDR0_CUST0_MUX_EMAC_SEL		0x40000000 /* Emac Selection */
+#define SDR0_CUST0_MUX_NDFC_SEL		0x80000000 /* NDFC Selection */
+#define SDR0_CUST0_MUX_GPIO_SEL		0xC0000000 /* GPIO Selection */
+
+#define SDR0_CUST0_NDFC_EN_MASK		0x20000000 /* NDFC Enable Mask */
+#define SDR0_CUST0_NDFC_ENABLE		0x20000000 /* NDFC Enable */
+#define SDR0_CUST0_NDFC_DISABLE		0x00000000 /* NDFC Disable */
+
+#define SDR0_CUST0_NDFC_BW_MASK		0x10000000 /* NDFC Boot Width */
+#define SDR0_CUST0_NDFC_BW_16_BIT	0x10000000 /* NDFC Boot Width = 16 Bit */
+#define SDR0_CUST0_NDFC_BW_8_BIT	0x00000000 /* NDFC Boot Width =  8 Bit */
+
+#define SDR0_CUST0_NDFC_BP_MASK		0x0F000000 /* NDFC Boot Page */
+#define SDR0_CUST0_NDFC_BP_ENCODE(n)	((((u32)(n)) & 0xF) << 24)
+#define SDR0_CUST0_NDFC_BP_DECODE(n)	((((u32)(n)) >> 24) & 0xF)
+
+#define SDR0_CUST0_NDFC_BAC_MASK	0x00C00000 /* NDFC Boot Address Cycle */
+#define SDR0_CUST0_NDFC_BAC_ENCODE(n)	((((u32)(n)) & 0x3) << 22)
+#define SDR0_CUST0_NDFC_BAC_DECODE(n)	((((u32)(n)) >> 22) & 0x3)
+
+#define SDR0_CUST0_NDFC_ARE_MASK	0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_ENABLE	0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_DISABLE	0x00000000 /* NDFC Auto Read Disable */
+
+#define SDR0_CUST0_NRB_MASK		0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY		0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY		0x00000000 /* Ready */
+
+#define SDR0_CUST0_NDRSC_MASK		0x0000FFF0 /* NDFC Device Reset Count Mask */
+#define SDR0_CUST0_NDRSC_ENCODE(n)	((((u32)(n)) & 0xFFF) << 4)
+#define SDR0_CUST0_NDRSC_DECODE(n)	((((u32)(n)) >> 4) & 0xFFF)
+
+#define SDR0_CUST0_CHIPSELGAT_MASK	0x0000000F /* Chip Select Gating Mask */
+#define SDR0_CUST0_CHIPSELGAT_DIS	0x00000000 /* Chip Select Gating Disable */
+#define SDR0_CUST0_CHIPSELGAT_ENALL	0x0000000F /*All Chip Select Gating Enable*/
+#define SDR0_CUST0_CHIPSELGAT_EN0	0x00000008 /* Chip Select0 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN1	0x00000004 /* Chip Select1 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN2	0x00000002 /* Chip Select2 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN3	0x00000001 /* Chip Select3 Gating Enable */
+
+#define SDR0_SRST_DMC			0x00200000
+
+#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
+#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
+#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
+#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
+#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
+#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
+#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
+
+#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
+#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
+#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
+#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
+#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
+#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
+
+#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
+#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PRADV_MASK		0x07000000  /* Primary Divisor A */
+#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
+#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
+
+/* Strap 1 Register */
+#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
+#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
+#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
+#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
+#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
+#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
+#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
+#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
+#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
+#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
+#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
+#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
+#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
+#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
+#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
+
+#define CPR0_ICFG_RLI_MASK	0x80000000
+#define CPR0_ICFG_ICS_MASK	0x00000007
+#define CPR0_SPCID_SPCIDV0_MASK	0x03000000
+#define CPR0_SPCID_SPCIDV0_DIV1	0x01000000
+#define CPR0_SPCID_SPCIDV0_DIV2	0x02000000
+#define CPR0_SPCID_SPCIDV0_DIV3	0x03000000
+#define CPR0_SPCID_SPCIDV0_DIV4	0x00000000
+#define CPR0_PERD_PERDV0_MASK	0x07000000
+
+#define PCI_MMIO_LCR_BASE	(CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
+								      0x0EF400000 */
+
+/* PCI Master Local Configuration Registers */
+#define PCIL0_PMM0LA		(PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
+#define PCIL0_PMM0MA		(PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
+#define PCIL0_PMM0PCILA		(PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
+#define PCIL0_PMM0PCIHA		(PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
+#define PCIL0_PMM1LA		(PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
+#define PCIL0_PMM1MA		(PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
+#define PCIL0_PMM1PCILA		(PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
+#define PCIL0_PMM1PCIHA		(PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
+#define PCIL0_PMM2LA		(PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
+#define PCIL0_PMM2MA		(PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
+#define PCIL0_PMM2PCILA		(PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
+#define PCIL0_PMM2PCIHA		(PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
+
+/* PCI Target Local Configuration Registers */
+#define PCIL0_PTM1MS		(PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
+							      Attribute */
+#define PCIL0_PTM1LA		(PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
+#define PCIL0_PTM2MS		(PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
+							      Attribute */
+#define PCIL0_PTM2LA		(PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
+
+#endif /* _PPC440EP_GR_H_ */
diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h
new file mode 100644
index 0000000..252f35b
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc440epx_grx.h
@@ -0,0 +1,464 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC440EPX_GRX_H_
+#define _PPC440EPX_GRX_H_
+
+#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2	/* Denali DDR(2) controller */
+
+#define CONFIG_NAND_NDFC
+
+/*
+ * Some SoC specific registers (not common for all 440 SoC's)
+ */
+
+/* Memory mapped registers */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
+
+#define SPI0_MODE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0090)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
+#define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
+
+/* DCR */
+#define CPM0_ER			0x00b0
+#define CPM1_ER			0x00f0
+#define PLB3A0_ACR		0x0077
+#define PLB4A0_ACR		0x0081
+#define PLB4A1_ACR		0x0089
+#define OPB2PLB40_BCTRL		0x0350
+#define P4P3BO0_CFG		0x0026
+
+/* SDR */
+#define SDR0_DDRCFG		0x00e0
+#define SDR0_PCI0		0x0300
+#define SDR0_SDSTP2		0x4001
+#define SDR0_SDSTP3		0x4003
+#define SDR0_EMAC0RXST 		0x4301
+#define SDR0_EMAC0TXST		0x4302
+#define SDR0_CRYP0		0x4500
+
+#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 21)
+#define SDR0_SDSTP1_PAME_MASK		(0x80000000 >> 27)
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1_U1ME_MASK		0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR		0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS		0x02000000 /* UART1 in CTS/RTS Mode */
+#define SDR0_PFC1_SELECT_MASK		0x01C00000 /* Ethernet Pin Select
+						      EMAC 0 */
+#define SDR0_PFC1_SELECT_CONFIG_1_1	0x00C00000 /* 1xMII   using RGMII
+						      bridge */
+#define SDR0_PFC1_SELECT_CONFIG_1_2	0x00000000 /* 1xMII   using  ZMII
+						      bridge */
+#define SDR0_PFC1_SELECT_CONFIG_2	0x00C00000 /* 1xGMII  using RGMII
+						      bridge */
+#define SDR0_PFC1_SELECT_CONFIG_3	0x01000000 /* 1xTBI   using RGMII
+						      bridge */
+#define SDR0_PFC1_SELECT_CONFIG_4	0x01400000 /* 2xRGMII using RGMII
+						      bridge */
+#define SDR0_PFC1_SELECT_CONFIG_5	0x01800000 /* 2xRTBI  using RGMII
+						      bridge */
+#define SDR0_PFC1_SELECT_CONFIG_6	0x00800000 /* 2xSMII  using  ZMII
+						      bridge */
+#define SDR0_PFC1_U0ME_MASK		0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR		0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS		0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK		0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS		0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS		0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK		0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL		0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL		0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK		0x00010000 /* USB2D_RX_Active / EBC_Hold
+						      Req Selection */
+#define SDR0_PFC1_UES_USB2D_SEL		0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL		0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK		0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
+						      Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL		0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL	0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK		0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
+						      Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL		0x00000000 /* EBC Mast.Ext.Req.En.
+						      Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL	0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK		0x00002000 /* USB2 Device Packet Reject
+						      Selection */
+#define SDR0_PFC1_UPR_DISABLE		0x00000000 /* USB2 Device Packet Reject
+						      Disable */
+#define SDR0_PFC1_UPR_ENABLE		0x00002000 /* USB2 Device Packet Reject
+						      Enable */
+#define SDR0_PFC1_PLB_PME_MASK		0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
+						      Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL	0x00000000 /* PLB3 Performance Monitor
+						      Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL	0x00001000 /* PLB3 Performance Monitor
+						      Enable */
+#define SDR0_PFC1_GFGGI_MASK		0x0000000F /* GPT Frequency Generation
+						      Gated In */
+
+#define SDR0_PFC2_SELECT_MASK		0xe0000000 /* Ethernet Pin select EMAC1 */
+#define SDR0_PFC2_SELECT_CONFIG_1_1	0x60000000 /* 1xMII   using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_1_2	0x00000000 /* 1xMII   using  ZMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_2	0x60000000 /* 1xGMII  using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_3	0x80000000 /* 1xTBI   using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_4	0xa0000000 /* 2xRGMII using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_5	0xc0000000 /* 2xRTBI  using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_6	0x40000000 /* 2xSMII  using  ZMII bridge */
+
+#define SDR0_USB2D0CR	0x0320
+#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC
+							 Master Selection */
+#define SDR0_USB2D0CR_USB2DEV_SELECTION	0x00000004 /* USB 2.0 Device Selection*/
+#define SDR0_USB2D0CR_EBC_SELECTION	0x00000000 /* EBC Selection */
+
+#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface
+							 Selection */
+#define SDR0_USB2D0CR_USB20D_DEVSEL	0x00000000 /* USB2.0 Device Selected */
+#define SDR0_USB2D0CR_USB11D_DEVSEL	0x00000002 /* USB1.1 Device Selected */
+
+#define SDR0_USB2D0CR_LEEN_MASK		0x00000001 /* Little Endian selection */
+#define SDR0_USB2D0CR_LEEN_DISABLE	0x00000000 /* Little Endian Disable */
+#define SDR0_USB2D0CR_LEEN_ENABLE	0x00000001 /* Little Endian Enable */
+
+/* USB2 Host Control Register */
+#define SDR0_USB2H0CR		0x0340
+#define SDR0_USB2H0CR_WDINT_MASK	0x00000001 /* Host UTMI Word Interface*/
+#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ	0x00000000 /* 8-bit/60MHz */
+#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ	0x00000001 /* 16-bit/30MHz */
+#define SDR0_USB2H0CR_EFLADJ_MASK	0x0000007e /* EHCI Frame Length
+						      Adjustment */
+/* USB2PHY0 Control Register */
+#define SDR0_USB2PHY0CR		0x4103
+#define SDR0_USB2PHY0CR_UTMICN_MASK	0x00100000
+
+	/*  PHY UTMI interface connection */
+#define SDR0_USB2PHY0CR_UTMICN_DEV	0x00000000 /* Device support */
+#define SDR0_USB2PHY0CR_UTMICN_HOST	0x00100000 /* Host support */
+
+#define SDR0_USB2PHY0CR_DWNSTR_MASK	0x00400000 /* Select downstream port mode */
+#define SDR0_USB2PHY0CR_DWNSTR_DEV	0x00000000 /* Device */
+#define SDR0_USB2PHY0CR_DWNSTR_HOST	0x00400000 /* Host   */
+
+/* VBus detect (Device mode only)  */
+#define SDR0_USB2PHY0CR_DVBUS_MASK	0x00800000
+/* Pull-up resistance on D+ is disabled */
+#define SDR0_USB2PHY0CR_DVBUS_PURDIS	0x00000000
+/* Pull-up resistance on D+ is enabled */
+#define SDR0_USB2PHY0CR_DVBUS_PUREN	0x00800000
+
+/* PHY UTMI data width and clock select  */
+#define SDR0_USB2PHY0CR_WDINT_MASK	0x01000000
+#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
+#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
+
+#define SDR0_USB2PHY0CR_LOOPEN_MASK	0x02000000 /* Loop back test enable  */
+#define SDR0_USB2PHY0CR_LOOP_ENABLE	0x00000000 /* Loop back disabled */
+/* Loop back enabled (only test purposes) */
+#define SDR0_USB2PHY0CR_LOOP_DISABLE	0x02000000
+
+/* Force XO block on during a suspend  */
+#define SDR0_USB2PHY0CR_XOON_MASK	0x04000000
+#define SDR0_USB2PHY0CR_XO_ON		0x00000000 /* PHY XO block is powered-on */
+/* PHY XO block is powered-off when all ports are suspended */
+#define SDR0_USB2PHY0CR_XO_OFF		0x04000000
+
+#define SDR0_USB2PHY0CR_PWRSAV_MASK	0x08000000 /* Select PHY power-save mode  */
+#define SDR0_USB2PHY0CR_PWRSAV_OFF	0x00000000 /* Non-power-save mode */
+#define SDR0_USB2PHY0CR_PWRSAV_ON	0x08000000 /* Power-save mode. Valid only
+						      for full-speed operation */
+
+#define SDR0_USB2PHY0CR_XOREF_MASK	0x10000000 /* Select reference clock
+						      source  */
+#define SDR0_USB2PHY0CR_XOREF_INTERNAL	0x00000000 /* PHY PLL uses chip internal
+						      48M clock as a reference */
+#define SDR0_USB2PHY0CR_XOREF_XO	0x10000000 /* PHY PLL uses internal XO
+						      block output as a reference */
+
+#define SDR0_USB2PHY0CR_XOCLK_MASK	0x20000000 /* Select clock for XO
+						      block*/
+#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL	0x00000000 /* PHY macro used an external
+						      clock */
+#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL	0x20000000 /* PHY macro uses the clock
+						      from a crystal */
+
+#define SDR0_USB2PHY0CR_CLKSEL_MASK	0xc0000000 /* Select ref clk freq */
+#define SDR0_USB2PHY0CR_CLKSEL_12MHZ	0x00000000 /* Select ref clk freq
+						      = 12 MHz */
+#define SDR0_USB2PHY0CR_CLKSEL_48MHZ	0x40000000 /* Select ref clk freq
+						      = 48 MHz */
+#define SDR0_USB2PHY0CR_CLKSEL_24MHZ	0x80000000 /* Select ref clk freq
+						      = 24 MHz */
+
+/* USB2.0 Device */
+/*
+ * todo: check if this can be completely removed, only used in
+ * cpu/ppc4xx/usbdev.c. And offsets are completely wrong. This could
+ * never have actually worked. Best probably is to remove this
+ * usbdev.c file completely (and these defines).
+ */
+#define USB2D0_BASE         CONFIG_SYS_USB2D0_BASE
+
+#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000)
+
+#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000) /* Interrupt register for
+				Endpoint 0 plus IN Endpoints 1 to 3 */
+#define USB2D0_POWER        (USB2D0_BASE + 0x00000000) /* Power management
+				register */
+#define USB2D0_FADDR        (USB2D0_BASE + 0x00000000) /* Function address
+				register */
+#define USB2D0_INTRINE      (USB2D0_BASE + 0x00000000) /* Interrupt enable
+				register for USB2D0_INTRIN */
+#define USB2D0_INTROUT      (USB2D0_BASE + 0x00000000) /* Interrupt register for
+				OUT Endpoints 1 to 3 */
+#define USB2D0_INTRUSBE     (USB2D0_BASE + 0x00000000) /* Interrupt enable
+				register for USB2D0_INTRUSB */
+#define USB2D0_INTRUSB      (USB2D0_BASE + 0x00000000) /* Interrupt register for
+				common USB interrupts */
+#define USB2D0_INTROUTE     (USB2D0_BASE + 0x00000000) /* Interrupt enable
+				register for IntrOut */
+#define USB2D0_TSTMODE      (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0
+				test modes */
+#define USB2D0_INDEX        (USB2D0_BASE + 0x00000000) /* Index register for
+			     selecting the Endpoint status/control registers */
+#define USB2D0_FRAME        (USB2D0_BASE + 0x00000000) /* Frame number */
+#define USB2D0_INCSR0       (USB2D0_BASE + 0x00000000) /* Control Status
+	  register for Endpoint 0. (Index register set to select Endpoint 0) */
+#define USB2D0_INCSR        (USB2D0_BASE + 0x00000000) /* Control Status
+       register for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_INMAXP       (USB2D0_BASE + 0x00000000) /* Maximum packet
+	   size for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCSR       (USB2D0_BASE + 0x00000000) /* Control Status
+      register for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTMAXP      (USB2D0_BASE + 0x00000000) /* Maximum packet
+	  size for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCOUNT0    (USB2D0_BASE + 0x00000000) /* Number of received
+	 bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
+#define USB2D0_OUTCOUNT     (USB2D0_BASE + 0x00000000) /* Number of bytes in
+	      OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
+
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR_ETH0_CLK_SEL_MASK	0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH0_CLK_SEL_EXT	0x00000000
+#define SDR0_MFR_ETH1_CLK_SEL_MASK	0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL_EXT	0x00000000
+#define SDR0_MFR_ZMII_MODE_MASK		0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII		0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII		0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_BIT0		0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1		0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ZM_ENCODE(n)		((((u32)(n)) & 0x3) << 24)
+#define SDR0_MFR_ZM_DECODE(n)		((((u32)(n)) << 24) & 0x3)
+#define SDR0_MFR_PKT_REJ_MASK		0x00300000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN		0x00300000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0		0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1		0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL		0x00080000 /* Packet Reject Polarity */
+
+/* CUST0 Customer Configuration Register0 */
+#define SDR0_CUST0_MUX_E_N_G_MASK	0xC0000000 /* Mux_Emac_NDFC_GPIO */
+#define SDR0_CUST0_MUX_EMAC_SEL		0x40000000 /* Emac Selection */
+#define SDR0_CUST0_MUX_NDFC_SEL		0x80000000 /* NDFC Selection */
+#define SDR0_CUST0_MUX_GPIO_SEL		0xC0000000 /* GPIO Selection */
+
+#define SDR0_CUST0_NDFC_EN_MASK		0x20000000 /* NDFC Enable Mask */
+#define SDR0_CUST0_NDFC_ENABLE		0x20000000 /* NDFC Enable */
+#define SDR0_CUST0_NDFC_DISABLE		0x00000000 /* NDFC Disable */
+
+#define SDR0_CUST0_NDFC_BW_MASK		0x10000000 /* NDFC Boot Width */
+#define SDR0_CUST0_NDFC_BW_16_BIT	0x10000000 /* NDFC Boot Width = 16 Bit */
+#define SDR0_CUST0_NDFC_BW_8_BIT	0x00000000 /* NDFC Boot Width =  8 Bit */
+
+#define SDR0_CUST0_NDFC_BP_MASK		0x0F000000 /* NDFC Boot Page */
+#define SDR0_CUST0_NDFC_BP_ENCODE(n)	((((u32)(n)) & 0xF) << 24)
+#define SDR0_CUST0_NDFC_BP_DECODE(n)	((((u32)(n)) >> 24) & 0xF)
+
+#define SDR0_CUST0_NDFC_BAC_MASK	0x00C00000 /* NDFC Boot Address Cycle */
+#define SDR0_CUST0_NDFC_BAC_ENCODE(n)	((((u32)(n)) & 0x3) << 22)
+#define SDR0_CUST0_NDFC_BAC_DECODE(n)	((((u32)(n)) >> 22) & 0x3)
+
+#define SDR0_CUST0_NDFC_ARE_MASK	0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_ENABLE	0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_DISABLE	0x00000000 /* NDFC Auto Read Disable */
+
+#define SDR0_CUST0_NRB_MASK		0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY		0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY		0x00000000 /* Ready */
+
+#define SDR0_CUST0_NDRSC_MASK		0x0000FFF0 /* NDFC Device Reset Count Mask */
+#define SDR0_CUST0_NDRSC_ENCODE(n)	((((u32)(n)) & 0xFFF) << 4)
+#define SDR0_CUST0_NDRSC_DECODE(n)	((((u32)(n)) >> 4) & 0xFFF)
+
+#define SDR0_CUST0_CHIPSELGAT_MASK	0x0000000F /* Chip Select Gating Mask */
+#define SDR0_CUST0_CHIPSELGAT_DIS	0x00000000 /* Chip Select Gating Disable */
+#define SDR0_CUST0_CHIPSELGAT_ENALL	0x0000000F /*All Chip Select Gating Enable*/
+#define SDR0_CUST0_CHIPSELGAT_EN0	0x00000008 /* Chip Select0 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN1	0x00000004 /* Chip Select1 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN2	0x00000002 /* Chip Select2 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN3	0x00000001 /* Chip Select3 Gating Enable */
+
+#define SDR0_SRST0_BGO		0x80000000 /* PLB to OPB bridge */
+#define SDR0_SRST0_PLB4		0x40000000 /* PLB4 arbiter */
+#define SDR0_SRST0_EBC		0x20000000 /* External bus controller */
+#define SDR0_SRST0_OPB		0x10000000 /* OPB arbiter */
+#define SDR0_SRST0_UART0	0x08000000 /* Universal asynchronous receiver/
+					      transmitter 0 */
+#define SDR0_SRST0_UART1	0x04000000 /* Universal asynchronous receiver/
+					      transmitter 1 */
+#define SDR0_SRST0_IIC0		0x02000000 /* Inter integrated circuit 0 */
+#define SDR0_SRST0_USB2H	0x01000000 /* USB2.0 Host */
+#define SDR0_SRST0_GPIO		0x00800000 /* General purpose I/O */
+#define SDR0_SRST0_GPT		0x00400000 /* General purpose timer */
+#define SDR0_SRST0_DMC		0x00200000 /* DDR SDRAM memory controller */
+#define SDR0_SRST0_PCI		0x00100000 /* PCI */
+#define SDR0_SRST0_EMAC0	0x00080000 /* Ethernet media access controller 0 */
+#define SDR0_SRST0_EMAC1	0x00040000 /* Ethernet media access controller 1 */
+#define SDR0_SRST0_CPM0		0x00020000 /* Clock and power management */
+#define SDR0_SRST0_ZMII		0x00010000 /* ZMII bridge */
+#define SDR0_SRST0_UIC0		0x00008000 /* Universal interrupt controller 0 */
+#define SDR0_SRST0_UIC1		0x00004000 /* Universal interrupt controller 1 */
+#define SDR0_SRST0_IIC1		0x00002000 /* Inter integrated circuit 1 */
+#define SDR0_SRST0_SCP		0x00001000 /* Serial communications port */
+#define SDR0_SRST0_BGI		0x00000800 /* OPB to PLB bridge */
+#define SDR0_SRST0_DMA		0x00000400 /* Direct memory access controller */
+#define SDR0_SRST0_DMAC		0x00000200 /* DMA channel */
+#define SDR0_SRST0_MAL		0x00000100 /* Media access layer */
+#define SDR0_SRST0_USB2D	0x00000080 /* USB2.0 device */
+#define SDR0_SRST0_GPTR		0x00000040 /* General purpose timer */
+#define SDR0_SRST0_P4P3		0x00000010 /* PLB4 to PLB3 bridge */
+#define SDR0_SRST0_P3P4		0x00000008 /* PLB3 to PLB4 bridge */
+#define SDR0_SRST0_PLB3		0x00000004 /* PLB3 arbiter */
+#define SDR0_SRST0_UART2	0x00000002 /* Universal asynchronous receiver/
+					      transmitter 2 */
+#define SDR0_SRST0_UART3	0x00000001 /* Universal asynchronous receiver/
+					      transmitter 3 */
+
+#define SDR0_SRST1_NDFC		0x80000000 /* Nand flash controller */
+#define SDR0_SRST1_OPBA1	0x40000000 /* OPB Arbiter attached to PLB4 */
+#define SDR0_SRST1_P4OPB0	0x20000000 /* PLB4 to OPB Bridge0 */
+#define SDR0_SRST1_PLB42OPB0	SDR0_SRST1_P4OPB0
+#define SDR0_SRST1_DMA4		0x10000000 /* DMA to PLB4 */
+#define SDR0_SRST1_DMA4CH	0x08000000 /* DMA Channel to PLB4 */
+#define SDR0_SRST1_OPBA2	0x04000000 /* OPB Arbiter attached to PLB4
+					      USB 2.0 Host */
+#define SDR0_SRST1_OPB2PLB40	0x02000000 /* OPB to PLB4 Bridge attached to
+					      USB 2.0 Host */
+#define SDR0_SRST1_PLB42OPB1	0x01000000 /* PLB4 to OPB Bridge attached to
+					      USB 2.0 Host */
+#define SDR0_SRST1_CPM1		0x00800000 /* Clock and Power management 1 */
+#define SDR0_SRST1_UIC2		0x00400000 /* Universal Interrupt Controller 2*/
+#define SDR0_SRST1_CRYP0	0x00200000 /* Security Engine */
+#define SDR0_SRST1_USB20PHY	0x00100000 /* USB 2.0 Phy */
+#define SDR0_SRST1_USB2HUTMI	0x00080000 /* USB 2.0 Host UTMI Interface */
+#define SDR0_SRST1_USB2HPHY	0x00040000 /* USB 2.0 Host Phy Interface */
+#define SDR0_SRST1_SRAM0	0x00020000 /* Internal SRAM Controller */
+#define SDR0_SRST1_RGMII0	0x00010000 /* RGMII Bridge */
+#define SDR0_SRST1_ETHPLL	0x00008000 /* Ethernet PLL */
+#define SDR0_SRST1_FPU 		0x00004000 /* Floating Point Unit */
+#define SDR0_SRST1_KASU0	0x00002000 /* Kasumi Engine */
+
+#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
+#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
+#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
+#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
+#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
+#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
+#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
+
+#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
+#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
+#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
+#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
+#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
+#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
+
+#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
+#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PRADV_MASK		0x07000000  /* Primary Divisor A */
+#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
+#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
+
+/* Strap 1 Register */
+#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
+#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
+#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
+#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
+#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
+#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
+#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
+#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
+#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
+#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
+#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
+#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
+#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
+#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
+#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
+
+#define CPR0_ICFG_RLI_MASK	0x80000000
+#define CPR0_ICFG_ICS_MASK	0x00000007
+#define CPR0_SPCID_SPCIDV0_MASK	0x03000000
+#define CPR0_SPCID_SPCIDV0_DIV1	0x01000000
+#define CPR0_SPCID_SPCIDV0_DIV2	0x02000000
+#define CPR0_SPCID_SPCIDV0_DIV3	0x03000000
+#define CPR0_SPCID_SPCIDV0_DIV4	0x00000000
+#define CPR0_PERD_PERDV0_MASK	0x07000000
+
+#define PCI_MMIO_LCR_BASE	(CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
+								      0x0EF400000 */
+
+/* PCI Master Local Configuration Registers */
+#define PCIL0_PMM0LA		(PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
+#define PCIL0_PMM0MA		(PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
+#define PCIL0_PMM0PCILA		(PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
+#define PCIL0_PMM0PCIHA		(PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
+#define PCIL0_PMM1LA		(PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
+#define PCIL0_PMM1MA		(PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
+#define PCIL0_PMM1PCILA		(PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
+#define PCIL0_PMM1PCIHA		(PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
+#define PCIL0_PMM2LA		(PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
+#define PCIL0_PMM2MA		(PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
+#define PCIL0_PMM2PCILA		(PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
+#define PCIL0_PMM2PCIHA		(PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
+
+/* PCI Target Local Configuration Registers */
+#define PCIL0_PTM1MS		(PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
+							      Attribute */
+#define PCIL0_PTM1LA		(PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
+#define PCIL0_PTM2MS		(PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
+							      Attribute */
+#define PCIL0_PTM2LA		(PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
+
+/* 440EPx boot strap options */
+#define BOOT_STRAP_OPTION_A	0x00000000
+#define BOOT_STRAP_OPTION_B	0x00000001
+#define BOOT_STRAP_OPTION_D	0x00000003
+#define BOOT_STRAP_OPTION_E	0x00000004
+
+#endif /* _PPC440EPX_GRX_H_ */
diff --git a/arch/powerpc/include/asm/ppc440gp.h b/arch/powerpc/include/asm/ppc440gp.h
new file mode 100644
index 0000000..3ebe2a1
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc440gp.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC440GP_H_
+#define _PPC440GP_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR	/* IBM DDR controller */
+
+/*
+ * Some SoC specific registers (not common for all 440 SoC's)
+ */
+
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xe0000000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+#define SDR0_PCI0	0x0300
+
+#define CPC0_STRP1_PAE_MASK		(0x80000000 >> 11)
+#define CPC0_STRP1_PISE_MASK		(0x80000000 >> 13)
+
+#define CNTRL_DCR_BASE	0x0b0
+
+#define CPC0_SYS0	(CNTRL_DCR_BASE + 0x30)	/* System configuration reg 0 */
+#define CPC0_SYS1	(CNTRL_DCR_BASE + 0x31)	/* System configuration reg 1 */
+
+#define CPC0_STRP0	(CNTRL_DCR_BASE + 0x34)	/* Power-on config reg 0 (RO) */
+#define CPC0_STRP1	(CNTRL_DCR_BASE + 0x35)	/* Power-on config reg 1 (RO) */
+
+#define CPC0_GPIO	(CNTRL_DCR_BASE + 0x38)	/* GPIO config reg (440GP) */
+
+#define CPC0_CR0	(CNTRL_DCR_BASE + 0x3b)	/* Control 0 register */
+#define CPC0_CR1	(CNTRL_DCR_BASE + 0x3a)	/* Control 1 register */
+
+#define PLLSYS0_TUNE_MASK	0xffc00000	/* PLL TUNE bits	    */
+#define PLLSYS0_FB_DIV_MASK	0x003c0000	/* Feedback divisor	    */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00038000	/* Forward divisor A	    */
+#define PLLSYS0_FWD_DIV_B_MASK	0x00007000	/* Forward divisor B	    */
+#define PLLSYS0_OPB_DIV_MASK	0x00000c00	/* OPB divisor		    */
+#define PLLSYS0_EPB_DIV_MASK	0x00000300	/* EPB divisor		    */
+#define PLLSYS0_EXTSL_MASK	0x00000080	/* PerClk feedback path	    */
+#define PLLSYS0_RW_MASK		0x00000060	/* ROM width		    */
+#define PLLSYS0_RL_MASK		0x00000010	/* ROM location		    */
+#define PLLSYS0_ZMII_SEL_MASK	0x0000000c	/* ZMII selection	    */
+#define PLLSYS0_BYPASS_MASK	0x00000002	/* Bypass PLL		    */
+#define PLLSYS0_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio	    */
+
+#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
+#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
+
+#endif /* _PPC440GP_H_ */
diff --git a/arch/powerpc/include/asm/ppc440gx.h b/arch/powerpc/include/asm/ppc440gx.h
new file mode 100644
index 0000000..6f8581b
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc440gx.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC440GX_H_
+#define _PPC440GX_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR	/* IBM DDR controller */
+
+/*
+ * Some SoC specific registers (not common for all 440 SoC's)
+ */
+
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xe0000000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+/* SDR's */
+#define SDR0_PCI0	0x0300
+
+#define SDR0_SDSTP2	0x4001
+#define SDR0_SDSTP3	0x4003
+
+#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
+#define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
+
+#define SDR0_PFC1_EPS_DECODE(n)		((((u32)(n)) >> 22) & 0x07)
+#define SDR0_PFC1_CTEMS_MASK		(0x80000000 >> 11)
+#define SDR0_PFC1_CTEMS_EMS		0x00000000
+#define SDR0_PFC1_CTEMS_CPUTRACE	(0x80000000 >> 11)
+
+#define SDR0_MFR_ECS_MASK		0x10000000
+
+#define SDR0_SRST_DMC			0x00200000
+
+#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
+#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
+#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
+#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
+#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
+#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
+#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
+
+#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
+#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
+#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
+#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
+#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
+#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
+
+#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
+#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PRADV_MASK		0x07000000  /* Primary Divisor A */
+#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
+#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
+
+/* Strap 1 Register */
+#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
+#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
+#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
+#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
+#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
+#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
+#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
+#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
+#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
+#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
+#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
+#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
+#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
+#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
+#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
+
+#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
+#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
+
+#endif /* _PPC440GX_H_ */
diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h
new file mode 100644
index 0000000..4387495
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc440sp.h
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC440SP_H_
+#define _PPC440SP_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
+
+/*
+ * Some SoC specific registers (not common for all 440 SoC's)
+ */
+
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xf0000000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+/* SDR's */
+#define SDR0_PCI0	0x0300
+#define SDR0_SDSTP2	0x0022
+#define SDR0_SDSTP3	0x0023
+
+#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
+#define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
+
+#define SDR0_PFC1_EM_1000		(0x80000000 >> 10)
+
+#define SDR0_MFR_FIXD			(0x80000000 >> 3)	/* Workaround for PCI/DMA */
+
+#define SDR0_SRST0_DMC			0x00200000
+
+#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
+#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
+#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
+#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
+#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
+#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
+#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
+
+#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
+#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
+#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
+#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
+#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
+#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
+
+#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
+#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PRADV_MASK		0x07000000  /* Primary Divisor A */
+#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
+#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
+
+/* Strap 1 Register */
+#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
+#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
+#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
+#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
+#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
+#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
+#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
+#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
+#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
+#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
+#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
+#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
+#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
+#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
+#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
+
+#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
+#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
+
+#endif /* _PPC440SP_H_ */
diff --git a/arch/powerpc/include/asm/ppc440spe.h b/arch/powerpc/include/asm/ppc440spe.h
new file mode 100644
index 0000000..bad9a40
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc440spe.h
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC440SPE_H_
+#define _PPC440SPE_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
+
+/*
+ * Some SoC specific registers (not common for all 440 SoC's)
+ */
+
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+/* SDR's */
+#define SDR0_PCI0	0x0300
+#define SDR0_SDSTP2	0x0022
+#define SDR0_SDSTP3	0x0023
+
+#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
+#define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
+#define SDR0_SDSTP1_ERPN_MASK		(0x80000000 >> 12)
+#define SDR0_SDSTP1_ERPN_EBC		0
+#define SDR0_SDSTP1_ERPN_PCI		(0x80000000 >> 12)
+#define SDR0_SDSTP1_EBCW_MASK		(0x80000000 >> 24)
+#define SDR0_SDSTP1_EBCW_8_BITS		0
+#define SDR0_SDSTP1_EBCW_16_BITS	(0x80000000 >> 24)
+
+#define SDR0_PFC1_EM_1000		(0x80000000 >> 10)
+
+#define SDR0_MFR_FIXD			(0x80000000 >> 3)	/* Workaround for PCI/DMA */
+
+#define SDR0_PINSTP_BOOTSTRAP_MASK	0xC0000000  /* Strap Bits */
+#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0	0x00000000  /* Default strap settings 0
+						       (EBC boot) */
+#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1	0x40000000  /* Default strap settings 1
+						       (PCI boot) */
+#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN	0x80000000  /* Serial Device Enabled -
+						       Addr = 0x54 */
+#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN	0xC0000000  /* Serial Device Enabled -
+						       Addr = 0x50 */
+
+#define SDR0_SRST0_DMC			0x00200000
+
+#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
+#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
+#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
+#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
+#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
+#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
+#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
+
+#define PLLC_ENG_MASK		0x20000000  /* PLL primary forward divisor source */
+#define PLLC_SRC_MASK		0x20000000  /* PLL feedback source   */
+#define PLLD_FBDV_MASK		0x1f000000  /* PLL Feedback Divisor  */
+#define PLLD_FWDVA_MASK		0x000f0000  /* PLL Forward Divisor A */
+#define PLLD_FWDVB_MASK		0x00000700  /* PLL Forward Divisor B */
+#define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
+
+#define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
+#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PRADV_MASK		0x07000000  /* Primary Divisor A */
+#define PRBDV_MASK		0x07000000  /* Primary Divisor B */
+#define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
+
+/* Strap 1 Register */
+#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
+#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
+#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
+#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
+#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
+#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
+#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
+#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
+#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
+#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
+#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
+#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
+#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
+#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
+#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
+
+#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
+#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
+
+#endif /* _PPC440SPE_H_ */
diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h
new file mode 100644
index 0000000..732fcac
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc460ex_gt.h
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC460EX_GT_H_
+#define _PPC460EX_GT_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
+
+#define CONFIG_NAND_NDFC
+
+/*
+ * Some SoC specific registers
+ */
+
+/* Memory mapped registers */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xef600000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
+#define GPIO1_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
+
+/* DCR */
+#define AHB_TOP			0x00a4
+#define AHB_BOT			0x00a5
+
+/* SDR */
+#define SDR0_PCI0		0x01c0
+#define SDR0_AHB_CFG		0x0370
+#define SDR0_USB2HOST_CFG	0x0371
+#define SDR0_ETH_PLL		0x4102
+#define SDR0_ETH_CFG		0x4103
+#define SDR0_ETH_STS		0x4104
+
+/*
+ * Register bits and masks
+ */
+#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
+#define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
+
+/* CUST0 Customer Configuration Register0 */
+#define SDR0_CUST0_MUX_E_N_G_MASK	0xC0000000 /* Mux_Emac_NDFC_GPIO */
+#define SDR0_CUST0_MUX_EMAC_SEL		0x40000000 /* Emac Selection */
+#define SDR0_CUST0_MUX_NDFC_SEL		0x80000000 /* NDFC Selection */
+#define SDR0_CUST0_MUX_GPIO_SEL		0xC0000000 /* GPIO Selection */
+
+#define SDR0_CUST0_NDFC_EN_MASK		0x20000000 /* NDFC Enable Mask */
+#define SDR0_CUST0_NDFC_ENABLE		0x20000000 /* NDFC Enable */
+#define SDR0_CUST0_NDFC_DISABLE		0x00000000 /* NDFC Disable */
+
+#define SDR0_CUST0_NDFC_BW_MASK		0x10000000 /* NDFC Boot Width */
+#define SDR0_CUST0_NDFC_BW_16_BIT	0x10000000 /* NDFC Boot Width = 16 Bit */
+#define SDR0_CUST0_NDFC_BW_8_BIT	0x00000000 /* NDFC Boot Width =  8 Bit */
+
+#define SDR0_CUST0_NDFC_BP_MASK		0x0F000000 /* NDFC Boot Page */
+#define SDR0_CUST0_NDFC_BP_ENCODE(n)	((((u32)(n)) & 0xF) << 24)
+#define SDR0_CUST0_NDFC_BP_DECODE(n)	((((u32)(n)) >> 24) & 0xF)
+
+#define SDR0_CUST0_NDFC_BAC_MASK	0x00C00000 /* NDFC Boot Address Cycle */
+#define SDR0_CUST0_NDFC_BAC_ENCODE(n)	((((u32)(n)) & 0x3) << 22)
+#define SDR0_CUST0_NDFC_BAC_DECODE(n)	((((u32)(n)) >> 22) & 0x3)
+
+#define SDR0_CUST0_NDFC_ARE_MASK	0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_ENABLE	0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_DISABLE	0x00000000 /* NDFC Auto Read Disable */
+
+#define SDR0_CUST0_NRB_MASK		0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY		0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY		0x00000000 /* Ready */
+
+#define SDR0_CUST0_NDRSC_MASK		0x0000FFF0 /* NDFC Device Reset Count Mask */
+#define SDR0_CUST0_NDRSC_ENCODE(n)	((((u32)(n)) & 0xFFF) << 4)
+#define SDR0_CUST0_NDRSC_DECODE(n)	((((u32)(n)) >> 4) & 0xFFF)
+
+#define SDR0_CUST0_CHIPSELGAT_MASK	0x0000000F /* Chip Select Gating Mask */
+#define SDR0_CUST0_CHIPSELGAT_DIS	0x00000000 /* Chip Select Gating Disable */
+#define SDR0_CUST0_CHIPSELGAT_ENALL	0x0000000F /*All Chip Select Gating Enable*/
+#define SDR0_CUST0_CHIPSELGAT_EN0	0x00000008 /* Chip Select0 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN1	0x00000004 /* Chip Select1 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN2	0x00000002 /* Chip Select2 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN3	0x00000001 /* Chip Select3 Gating Enable */
+
+/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
+#define SDR0_ETH_PLL_PLLLOCK	0x80000000	/* Ethernet PLL lock indication */
+
+/* Ethernet Configuration Register (SDR0_ETH_CFG) */
+#define SDR0_ETH_CFG_SGMII3_LPBK	0x00800000 /*SGMII3 port loopback
+						    enable */
+#define SDR0_ETH_CFG_SGMII2_LPBK	0x00400000 /*SGMII2 port loopback
+						    enable */
+#define SDR0_ETH_CFG_SGMII1_LPBK	0x00200000 /*SGMII1 port loopback
+						    enable */
+#define SDR0_ETH_CFG_SGMII0_LPBK	0x00100000 /*SGMII0 port loopback
+						    enable */
+#define SDR0_ETH_CFG_SGMII_MASK		0x00070000 /*SGMII Mask */
+#define SDR0_ETH_CFG_SGMII2_ENABLE	0x00040000 /*SGMII2 port enable */
+#define SDR0_ETH_CFG_SGMII1_ENABLE	0x00020000 /*SGMII1 port enable */
+#define SDR0_ETH_CFG_SGMII0_ENABLE	0x00010000 /*SGMII0 port enable */
+#define SDR0_ETH_CFG_TAHOE1_BYPASS	0x00002000 /*TAHOE1 Bypass selector */
+#define SDR0_ETH_CFG_TAHOE0_BYPASS	0x00001000 /*TAHOE0 Bypass selector */
+#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL	0x00000800 /*EMAC 3 PHY clock selector*/
+#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL	0x00000400 /*EMAC 2 PHY clock selector*/
+#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL	0x00000200 /*EMAC 1 PHY clock selector*/
+#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL	0x00000100 /*EMAC 0 PHY clock selector*/
+#define SDR0_ETH_CFG_EMAC_2_1_SWAP	0x00000080 /*Swap EMAC2 with EMAC1 */
+#define SDR0_ETH_CFG_EMAC_0_3_SWAP	0x00000040 /*Swap EMAC0 with EMAC3 */
+#define SDR0_ETH_CFG_MDIO_SEL_MASK	0x00000030 /*MDIO source selector mask*/
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC0	0x00000000 /*MDIO source - EMAC0 */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC1	0x00000010 /*MDIO source - EMAC1 */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC2	0x00000020 /*MDIO source - EMAC2 */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC3	0x00000030 /*MDIO source - EMAC3 */
+#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL	0x00000002 /*GMC Port 1 bridge
+						     selector */
+#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL	0x00000001 /*GMC Port 0 bridge
+						    selector */
+
+#define SDR0_SRST0_BGO		0x80000000 /* PLB to OPB bridge */
+#define SDR0_SRST0_PLB4		0x40000000 /* PLB4 arbiter */
+#define SDR0_SRST0_EBC		0x20000000 /* External bus controller */
+#define SDR0_SRST0_OPB		0x10000000 /* OPB arbiter */
+#define SDR0_SRST0_UART0	0x08000000 /* Universal asynchronous receiver/
+					      transmitter 0 */
+#define SDR0_SRST0_UART1	0x04000000 /* Universal asynchronous receiver/
+					      transmitter 1 */
+#define SDR0_SRST0_IIC0		0x02000000 /* Inter integrated circuit 0 */
+#define SDR0_SRST0_IIC1		0x01000000 /* Inter integrated circuit 1 */
+#define SDR0_SRST0_GPIO0	0x00800000 /* General purpose I/O 0 */
+#define SDR0_SRST0_GPT		0x00400000 /* General purpose timer */
+#define SDR0_SRST0_DMC		0x00200000 /* DDR SDRAM memory controller */
+#define SDR0_SRST0_PCI		0x00100000 /* PCI */
+#define SDR0_SRST0_CPM0		0x00020000 /* Clock and power management */
+#define SDR0_SRST0_IMU		0x00010000 /* I2O DMA */
+#define SDR0_SRST0_UIC0		0x00008000 /* Universal interrupt controller 0*/
+#define SDR0_SRST0_UIC1		0x00004000 /* Universal interrupt controller 1*/
+#define SDR0_SRST0_SRAM		0x00002000 /* Universal interrupt controller 0*/
+#define SDR0_SRST0_UIC2		0x00001000 /* Universal interrupt controller 2*/
+#define SDR0_SRST0_UIC3		0x00000800 /* Universal interrupt controller 3*/
+#define SDR0_SRST0_OCM		0x00000400 /* Universal interrupt controller 0*/
+#define SDR0_SRST0_UART2	0x00000200 /* Universal asynchronous receiver/
+					      transmitter 2 */
+#define SDR0_SRST0_MAL		0x00000100 /* Media access layer */
+#define SDR0_SRST0_GPTR         0x00000040 /* General purpose timer */
+#define SDR0_SRST0_L2CACHE	0x00000004 /* L2 Cache */
+#define SDR0_SRST0_UART3	0x00000002 /* Universal asynchronous receiver/
+					      transmitter 3 */
+#define SDR0_SRST0_GPIO1	0x00000001 /* General purpose I/O 1 */
+
+#define SDR0_SRST1_RLL		0x80000000 /* SRIO RLL */
+#define SDR0_SRST1_SCP		0x40000000 /* Serial communications port */
+#define SDR0_SRST1_PLBARB	0x20000000 /* PLB Arbiter */
+#define SDR0_SRST1_EIPPKP	0x10000000 /* EIPPPKP */
+#define SDR0_SRST1_EIP94	0x08000000 /* EIP 94 */
+#define SDR0_SRST1_EMAC0	0x04000000 /* Ethernet media access
+					      controller 0 */
+#define SDR0_SRST1_EMAC1	0x02000000 /* Ethernet media access
+					      controller 1 */
+#define SDR0_SRST1_EMAC2	0x01000000 /* Ethernet media access
+					      controller 2 */
+#define SDR0_SRST1_EMAC3	0x00800000 /* Ethernet media access
+					      controller 3 */
+#define SDR0_SRST1_ZMII		0x00400000 /* Ethernet ZMII/RMII/SMII */
+#define SDR0_SRST1_RGMII0	0x00200000 /* Ethernet RGMII/RTBI 0 */
+#define SDR0_SRST1_RGMII1	0x00100000 /* Ethernet RGMII/RTBI 1 */
+#define SDR0_SRST1_DMA4		0x00080000 /* DMA to PLB4 */
+#define SDR0_SRST1_DMA4CH	0x00040000 /* DMA Channel to PLB4 */
+#define SDR0_SRST1_SATAPHY	0x00020000 /* Serial ATA PHY */
+#define SDR0_SRST1_SRIODEV	0x00010000 /* Serial Rapid IO core, PCS, and
+					      serdes */
+#define SDR0_SRST1_SRIOPCS	0x00008000 /* Serial Rapid IO core and PCS */
+#define SDR0_SRST1_NDFC		0x00004000 /* Nand flash controller */
+#define SDR0_SRST1_SRIOPLB	0x00002000 /* Serial Rapid IO PLB */
+#define SDR0_SRST1_ETHPLL	0x00001000 /* Ethernet PLL */
+#define SDR0_SRST1_TAHOE1	0x00000800 /* Ethernet Tahoe 1 */
+#define SDR0_SRST1_TAHOE0	0x00000400 /* Ethernet Tahoe 0 */
+#define SDR0_SRST1_SGMII0	0x00000200 /* Ethernet SGMII 0 */
+#define SDR0_SRST1_SGMII1	0x00000100 /* Ethernet SGMII 1 */
+#define SDR0_SRST1_SGMII2	0x00000080 /* Ethernet SGMII 2 */
+#define SDR0_SRST1_AHB		0x00000040 /* PLB4XAHB bridge */
+#define SDR0_SRST1_USBOTGPHY	0x00000020 /* USB 2.0 OTG PHY */
+#define SDR0_SRST1_USBOTG	0x00000010 /* USB 2.0 OTG controller */
+#define SDR0_SRST1_USBHOST	0x00000008 /* USB 2.0 Host controller */
+#define SDR0_SRST1_AHBDMAC	0x00000004 /* AHB DMA controller */
+#define SDR0_SRST1_AHBICM	0x00000002 /* AHB inter-connect matrix */
+#define SDR0_SRST1_SATA		0x00000001 /* Serial ATA controller */
+
+#define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
+#define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
+#define PLLSYS0_OPB_DIV_MASK	0x0c000000	/* OPB Divisor */
+#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000	/* PLB Early Clock Divisor */
+#define PLLSYS0_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS0_SEL_MASK	0x18000000	/* 0 = PLL, 1 = PerClk */
+
+#define CPR0_ICFG_RLI_MASK	0x80000000
+
+#define CPR0_PLLC_RST		0x80000000
+#define CPR0_PLLC_ENG		0x40000000
+
+#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
+#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
+
+#endif /* _PPC460EX_GT_H_ */
diff --git a/arch/powerpc/include/asm/ppc460sx.h b/arch/powerpc/include/asm/ppc460sx.h
new file mode 100644
index 0000000..f93ef0e
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc460sx.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC460SX_H_
+#define _PPC460SX_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
+
+/* Memory mapped registers */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+#define SDR0_SRST0_DMC			0x00200000
+
+#define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
+#define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
+#define PLLSYS0_OPB_DIV_MASK	0x0c000000	/* OPB Divisor */
+#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000	/* PLB Early Clock Divisor */
+#define PLLSYS0_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS0_SEL_MASK	0x18000000	/* 0 = PLL, 1 = PerClk */
+
+#endif /* _PPC460SX_H_ */
diff --git a/arch/powerpc/include/asm/ppc4xx-emac.h b/arch/powerpc/include/asm/ppc4xx-emac.h
new file mode 100644
index 0000000..25a0512
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc4xx-emac.h
@@ -0,0 +1,556 @@
+/*----------------------------------------------------------------------------+
+|   This source code is dual-licensed.  You may use it under the terms of the
+|   GNU General Public License version 2, or under the license below.
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|
+|  File Name:	enetemac.h
+|
+|  Function:	Header file for the EMAC3 macro on the 405GP.
+|
+|  Author:	Mark Wisner
+|
+|  Change Activity-
+|
+|  Date	       Description of Change					   BY
+|  ---------   ---------------------					   ---
+|  29-Apr-99   Created							   MKW
+|
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|  19-Nov-03   Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+|	       ported to handle 440GP and 440GX multiple EMACs
++----------------------------------------------------------------------------*/
+
+#ifndef _PPC4XX_ENET_H_
+#define _PPC4XX_ENET_H_
+
+#include <net.h>
+#include "asm/ppc4xx-mal.h"
+
+
+/*-----------------------------------------------------------------------------+
+| General enternet defines.  802 frames are not supported.
++-----------------------------------------------------------------------------*/
+#define ENET_ADDR_LENGTH		6
+#define ENET_ARPTYPE			0x806
+#define ARP_REQUEST			1
+#define ARP_REPLY			2
+#define ENET_IPTYPE			0x800
+#define ARP_CACHE_SIZE			5
+
+#define NUM_TX_BUFF 1
+#define NUM_RX_BUFF PKTBUFSRX
+
+struct enet_frame {
+   unsigned char	dest_addr[ENET_ADDR_LENGTH];
+   unsigned char	source_addr[ENET_ADDR_LENGTH];
+   unsigned short	type;
+   unsigned char	enet_data[1];
+};
+
+struct arp_entry {
+   unsigned long	inet_address;
+   unsigned char	mac_address[ENET_ADDR_LENGTH];
+   unsigned long	valid;
+   unsigned long	sec;
+   unsigned long	nsec;
+};
+
+
+/* Statistic Areas */
+#define MAX_ERR_LOG 10
+
+typedef struct emac_stats_st{	/* Statistic Block */
+	int data_len_err;
+	int rx_frames;
+	int rx;
+	int rx_prot_err;
+	int int_err;
+	int pkts_tx;
+	int pkts_rx;
+	int pkts_handled;
+	short tx_err_log[MAX_ERR_LOG];
+	short rx_err_log[MAX_ERR_LOG];
+} EMAC_STATS_ST, *EMAC_STATS_PST;
+
+/* Structure containing variables used by the shared code (4xx_enet.c) */
+typedef struct emac_4xx_hw_st {
+    uint32_t		hw_addr;		/* EMAC offset */
+    uint32_t		tah_addr;		/* TAH offset */
+    uint32_t		phy_id;
+    uint32_t		phy_addr;
+    uint32_t		original_fc;
+    uint32_t		txcw;
+    uint32_t		autoneg_failed;
+    uint32_t		emac_ier;
+    volatile mal_desc_t *tx;
+    volatile mal_desc_t *rx;
+    u32			tx_phys;
+    u32			rx_phys;
+    bd_t		*bis;	/* for eth_init upon mal error */
+    mal_desc_t		*alloc_tx_buf;
+    mal_desc_t		*alloc_rx_buf;
+    char		*txbuf_ptr;
+    uint16_t		devnum;
+    int			get_link_status;
+    int			tbi_compatibility_en;
+    int			tbi_compatibility_on;
+    int			fc_send_xon;
+    int			report_tx_early;
+    int			first_init;
+    int			tx_err_index;
+    int			rx_err_index;
+    int			rx_slot;	/* MAL Receive Slot */
+    int			rx_i_index;	/* Receive Interrupt Queue Index */
+    int			rx_u_index;	/* Receive User Queue Index */
+    int			tx_slot;	/* MAL Transmit Slot */
+    int			tx_i_index;	/* Transmit Interrupt Queue Index */
+    int			tx_u_index;		/* Transmit User Queue Index */
+    int			rx_ready[NUM_RX_BUFF];	/* Receive Ready Queue */
+    int			tx_run[NUM_TX_BUFF];	/* Transmit Running Queue */
+    int			is_receiving;	/* sync with eth interrupt */
+    int			print_speed;	/* print speed message upon start */
+    EMAC_STATS_ST	stats;
+} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
+
+
+#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
+#define EMAC_NUM_DEV		4
+#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) &&	\
+	defined(CONFIG_NET_MULTI) &&			\
+	!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#define EMAC_NUM_DEV		2
+#else
+#define EMAC_NUM_DEV		1
+#endif
+
+#ifdef CONFIG_IBM_EMAC4_V4	/* EMAC4 V4 changed bit setting */
+#define EMAC_STACR_OC_MASK	(0x00008000)
+#else
+#define EMAC_STACR_OC_MASK	(0x00000000)
+#endif
+
+/*
+ * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
+ * not have a pin function control (PFC) register to otherwise determine
+ * the bridge configuration.
+ */
+#define EMAC_PHY_MODE_NONE		0
+#define EMAC_PHY_MODE_NONE_RGMII	1
+#define EMAC_PHY_MODE_RGMII_NONE	2
+#define EMAC_PHY_MODE_RGMII_RGMII	3
+#define EMAC_PHY_MODE_NONE_GMII		4
+#define EMAC_PHY_MODE_GMII_NONE		5
+#define EMAC_PHY_MODE_NONE_MII		6
+#define EMAC_PHY_MODE_MII_NONE		7
+
+/* ZMII Bridge Register addresses */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define ZMII0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
+#else
+#define ZMII0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
+#endif
+#define ZMII0_FER		(ZMII0_BASE)
+#define ZMII0_SSR		(ZMII0_BASE + 4)
+#define ZMII0_SMIISR		(ZMII0_BASE + 8)
+
+/* ZMII FER Register Bit Definitions */
+#define ZMII_FER_DIS		(0x0)
+#define ZMII_FER_MDI		(0x8)
+#define ZMII_FER_SMII		(0x4)
+#define ZMII_FER_RMII		(0x2)
+#define ZMII_FER_MII		(0x1)
+
+#define ZMII_FER_RSVD11		(0x00200000)
+#define ZMII_FER_RSVD10		(0x00100000)
+#define ZMII_FER_RSVD14_31	(0x0003FFFF)
+
+#define ZMII_FER_V(__x)		(((3 - __x) * 4) + 16)
+
+
+/* ZMII Speed Selection Register Bit Definitions */
+#define ZMII0_SSR_SCI		(0x4)
+#define ZMII0_SSR_FSS		(0x2)
+#define ZMII0_SSR_SP		(0x1)
+#define ZMII0_SSR_RSVD16_31	(0x0000FFFF)
+
+#define ZMII0_SSR_V(__x)		(((3 - __x) * 4) + 16)
+
+
+/* ZMII SMII Status Register Bit Definitions */
+#define ZMII0_SMIISR_E1		(0x80)
+#define ZMII0_SMIISR_EC		(0x40)
+#define ZMII0_SMIISR_EN		(0x20)
+#define ZMII0_SMIISR_EJ		(0x10)
+#define ZMII0_SMIISR_EL		(0x08)
+#define ZMII0_SMIISR_ED		(0x04)
+#define ZMII0_SMIISR_ES		(0x02)
+#define ZMII0_SMIISR_EF		(0x01)
+
+#define ZMII0_SMIISR_V(__x)	((3 - __x) * 8)
+
+/* RGMII Register Addresses */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
+#elif defined(CONFIG_405EX)
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
+#else
+#define RGMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
+#endif
+#define RGMII_FER		(RGMII_BASE + 0x00)
+#define RGMII_SSR		(RGMII_BASE + 0x04)
+
+#if defined(CONFIG_460GT)
+#define RGMII1_BASE_OFFSET	0x100
+#endif
+
+/* RGMII Function Enable (FER) Register Bit Definitions */
+#define RGMII_FER_DIS		(0x00)
+#define RGMII_FER_RTBI		(0x04)
+#define RGMII_FER_RGMII		(0x05)
+#define RGMII_FER_TBI		(0x06)
+#define RGMII_FER_GMII		(0x07)
+#define RGMII_FER_MII		(RGMII_FER_GMII)
+
+#define RGMII_FER_V(__x)	((__x - 2) * 4)
+
+#define RGMII_FER_MDIO(__x)	(1 << (19 - (__x)))
+
+/* RGMII Speed Selection Register Bit Definitions */
+#define RGMII_SSR_SP_10MBPS	(0x00)
+#define RGMII_SSR_SP_100MBPS	(0x02)
+#define RGMII_SSR_SP_1000MBPS	(0x04)
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+#define RGMII_SSR_V(__x)	((__x) * 8)
+#else
+#define RGMII_SSR_V(__x)	((__x -2) * 8)
+#endif
+
+/*---------------------------------------------------------------------------+
+|  TCP/IP Acceleration Hardware (TAH) 440GX Only
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440GX)
+#define TAH_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
+#define TAH_REVID	(TAH_BASE + 0x0)    /* Revision ID (RO)*/
+#define TAH_MR		(TAH_BASE + 0x10)   /* Mode Register (R/W) */
+#define TAH_SSR0	(TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
+#define TAH_SSR1	(TAH_BASE + 0x18)   /* Segment Size Reg 1 (R/W) */
+#define TAH_SSR2	(TAH_BASE + 0x1C)   /* Segment Size Reg 2 (R/W) */
+#define TAH_SSR3	(TAH_BASE + 0x20)   /* Segment Size Reg 3 (R/W) */
+#define TAH_SSR4	(TAH_BASE + 0x24)   /* Segment Size Reg 4 (R/W) */
+#define TAH_SSR5	(TAH_BASE + 0x28)   /* Segment Size Reg 5 (R/W) */
+#define TAH_TSR		(TAH_BASE + 0x2C)   /* Transmit Status Register (RO) */
+
+/* TAH Revision */
+#define TAH_REV_RN_M		(0x000FFF00)	    /* Revision Number */
+#define TAH_REV_BN_M		(0x000000FF)	    /* Branch Revision Number */
+
+#define TAH_REV_RN_V		(8)
+#define TAH_REV_BN_V		(0)
+
+/* TAH Mode Register */
+#define TAH_MR_CVR	(0x80000000)	    /* Checksum verification on RX */
+#define TAH_MR_SR	(0x40000000)	    /* Software reset */
+#define TAH_MR_ST	(0x3F000000)	    /* Send Threshold */
+#define TAH_MR_TFS	(0x00E00000)	    /* Transmit FIFO size */
+#define TAH_MR_DTFP	(0x00100000)	    /* Disable TX FIFO parity */
+#define TAH_MR_DIG	(0x00080000)	    /* Disable interrupt generation */
+#define TAH_MR_RSVD	(0x0007FFFF)	    /* Reserved */
+
+#define TAH_MR_ST_V	(20)
+#define TAH_MR_TFS_V	(17)
+
+#define TAH_MR_TFS_2K	(0x1)	    /* Transmit FIFO size 2Kbyte */
+#define TAH_MR_TFS_4K	(0x2)	    /* Transmit FIFO size 4Kbyte */
+#define TAH_MR_TFS_6K	(0x3)	    /* Transmit FIFO size 6Kbyte */
+#define TAH_MR_TFS_8K	(0x4)	    /* Transmit FIFO size 8Kbyte */
+#define TAH_MR_TFS_10K	(0x5)	    /* Transmit FIFO size 10Kbyte (max)*/
+
+
+/* TAH Segment Size Registers 0:5 */
+#define TAH_SSR_RSVD0	(0xC0000000)	    /* Reserved */
+#define TAH_SSR_SS	(0x3FFE0000)	    /* Segment size in multiples of 2 */
+#define TAH_SSR_RSVD1	(0x0001FFFF)	    /* Reserved */
+
+/* TAH Transmit Status Register */
+#define TAH_TSR_TFTS	(0x80000000)	    /* Transmit FIFO too small */
+#define TAH_TSR_UH	(0x40000000)	    /* Unrecognized header */
+#define TAH_TSR_NIPF	(0x20000000)	    /* Not IPv4 */
+#define TAH_TSR_IPOP	(0x10000000)	    /* IP option present */
+#define TAH_TSR_NISF	(0x08000000)	    /* No IEEE SNAP format */
+#define TAH_TSR_ILTS	(0x04000000)	    /* IP length too short */
+#define TAH_TSR_IPFP	(0x02000000)	    /* IP fragment present */
+#define TAH_TSR_UP	(0x01000000)	    /* Unsupported protocol */
+#define TAH_TSR_TFP	(0x00800000)	    /* TCP flags present */
+#define TAH_TSR_SUDP	(0x00400000)	    /* Segmentation for UDP */
+#define TAH_TSR_DLM	(0x00200000)	    /* Data length mismatch */
+#define TAH_TSR_SIEEE	(0x00100000)	    /* Segmentation for IEEE */
+#define TAH_TSR_TFPE	(0x00080000)	    /* Transmit FIFO parity error */
+#define TAH_TSR_SSTS	(0x00040000)	    /* Segment size too small */
+#define TAH_TSR_RSVD	(0x0003FFFF)	    /* Reserved */
+#endif /* CONFIG_440GX */
+
+
+/* Ethernet MAC Regsiter Addresses */
+#if defined(CONFIG_440)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define EMAC0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
+#else
+#define EMAC0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
+#endif
+#else
+#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
+#define EMAC0_BASE		0xEF600900
+#else
+#define EMAC0_BASE		0xEF600800
+#endif
+#endif
+
+#if defined(CONFIG_440EPX)
+#define EMAC1_BASE		0xEF600F00
+#define EMAC1_MR1		(EMAC1_BASE + 0x04)
+#endif
+
+#define EMAC0_MR0		(EMAC0_BASE)
+#define EMAC0_MR1		(EMAC0_BASE + 0x04)
+#define EMAC0_TMR0		(EMAC0_BASE + 0x08)
+#define EMAC0_TMR1		(EMAC0_BASE + 0x0c)
+#define EMAC0_RXM		(EMAC0_BASE + 0x10)
+#define EMAC0_ISR		(EMAC0_BASE + 0x14)
+#define EMAC0_IER		(EMAC0_BASE + 0x18)
+#define EMAC0_IAH		(EMAC0_BASE + 0x1c)
+#define EMAC0_IAL		(EMAC0_BASE + 0x20)
+#define EMAC0_PTR		(EMAC0_BASE + 0x2c)
+#define EMAC0_PAUSE_TIME_REG	EMAC0_PTR
+#define EMAC0_IPGVR		(EMAC0_BASE + 0x58)
+#define EMAC0_I_FRAME_GAP_REG	EMAC0_IPGVR
+#define EMAC0_STACR		(EMAC0_BASE + 0x5c)
+#define EMAC0_TRTR		(EMAC0_BASE + 0x60)
+#define EMAC0_RWMR		(EMAC0_BASE + 0x64)
+#define EMAC0_RX_HI_LO_WMARK	EMAC0_RWMR
+
+/* bit definitions */
+/* MODE REG 0 */
+#define EMAC_MR0_RXI		(0x80000000)
+#define EMAC_MR0_TXI		(0x40000000)
+#define EMAC_MR0_SRST		(0x20000000)
+#define EMAC_MR0_TXE		(0x10000000)
+#define EMAC_MR0_RXE		(0x08000000)
+#define EMAC_MR0_WKE		(0x04000000)
+
+/* on 440GX EMAC_MR1 has a different layout! */
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+/* MODE Reg 1 */
+#define EMAC_MR1_FDE		(0x80000000)
+#define EMAC_MR1_ILE		(0x40000000)
+#define EMAC_MR1_VLE		(0x20000000)
+#define EMAC_MR1_EIFC		(0x10000000)
+#define EMAC_MR1_APP		(0x08000000)
+#define EMAC_MR1_RSVD		(0x06000000)
+#define EMAC_MR1_IST		(0x01000000)
+#define EMAC_MR1_MF_1000GPCS	(0x00C00000)
+#define EMAC_MR1_MF_1000MBPS	(0x00800000)	/* 0's for 10MBPS */
+#define EMAC_MR1_MF_100MBPS	(0x00400000)
+#define EMAC_MR1_RFS_MASK	(0x00380000)
+#define EMAC_MR1_RFS_16K		(0x00280000)
+#define EMAC_MR1_RFS_8K		(0x00200000)
+#define EMAC_MR1_RFS_4K		(0x00180000)
+#define EMAC_MR1_RFS_2K		(0x00100000)
+#define EMAC_MR1_RFS_1K		(0x00080000)
+#define EMAC_MR1_TX_FIFO_MASK	(0x00070000)
+#define EMAC_MR1_TX_FIFO_16K	(0x00050000)
+#define EMAC_MR1_TX_FIFO_8K	(0x00040000)
+#define EMAC_MR1_TX_FIFO_4K	(0x00030000)
+#define EMAC_MR1_TX_FIFO_2K	(0x00020000)
+#define EMAC_MR1_TX_FIFO_1K	(0x00010000)
+#define EMAC_MR1_TR_MULTI	(0x00008000)	/* 0'x for single packet */
+#define EMAC_MR1_MWSW		(0x00007000)
+#define EMAC_MR1_JUMBO_ENABLE	(0x00000800)
+#define EMAC_MR1_IPPA		(0x000007c0)
+#define EMAC_MR1_IPPA_SET(id)	(((id) & 0x1f) << 6)
+#define EMAC_MR1_IPPA_GET(id)	(((id) >> 6) & 0x1f)
+#define EMAC_MR1_OBCI_GT100	(0x00000020)
+#define EMAC_MR1_OBCI_100	(0x00000018)
+#define EMAC_MR1_OBCI_83		(0x00000010)
+#define EMAC_MR1_OBCI_66		(0x00000008)
+#define EMAC_MR1_RSVD1		(0x00000007)
+#else /* defined(CONFIG_440GX) */
+/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
+#define EMAC_MR1_FDE		0x80000000
+#define EMAC_MR1_ILE		0x40000000
+#define EMAC_MR1_VLE		0x20000000
+#define EMAC_MR1_EIFC		0x10000000
+#define EMAC_MR1_APP		0x08000000
+#define EMAC_MR1_AEMI		0x02000000
+#define EMAC_MR1_IST		0x01000000
+#define EMAC_MR1_MF_1000MBPS	0x00800000	/* 0's for 10MBPS */
+#define EMAC_MR1_MF_100MBPS	0x00400000
+#define EMAC_MR1_RFS_MASK	0x00300000
+#define EMAC_MR1_RFS_4K		0x00300000
+#define EMAC_MR1_RFS_2K		0x00200000
+#define EMAC_MR1_RFS_1K		0x00100000
+#define EMAC_MR1_RFS_512		0x00000000
+#define EMAC_MR1_TX_FIFO_MASK	0x000c0000
+#define EMAC_MR1_TX_FIFO_2K	0x00080000
+#define EMAC_MR1_TX_FIFO_1K	0x00040000
+#define EMAC_MR1_TX_FIFO_512	0x00000000
+#define EMAC_MR1_TR0_DEPEND	0x00010000	/* 0'x for single packet */
+#define EMAC_MR1_TR0_MULTI	0x00008000
+#define EMAC_MR1_TR1_DEPEND	0x00004000
+#define EMAC_MR1_TR1_MULTI	0x00002000
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define EMAC_MR1_JUMBO_ENABLE	0x00001000
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#endif /* defined(CONFIG_440GX) */
+
+#define EMAC_MR1_FIFO_MASK	(EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
+#if defined(CONFIG_405EZ)
+/* 405EZ only supports 512 bytes fifos */
+#define EMAC_MR1_FIFO_SIZE	(EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
+#else
+/* Set receive fifo to 4k and tx fifo to 2k */
+#define EMAC_MR1_FIFO_SIZE	(EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
+#endif
+
+/* Transmit Mode Register 0 */
+#define EMAC_TMR0_GNP0		(0x80000000)
+#define EMAC_TMR0_GNP1		(0x40000000)
+#define EMAC_TMR0_GNPD		(0x20000000)
+#define EMAC_TMR0_FC		(0x10000000)
+
+/* Receive Mode Register */
+#define EMAC_RMR_SP		(0x80000000)
+#define EMAC_RMR_SFCS		(0x40000000)
+#define EMAC_RMR_ARRP		(0x20000000)
+#define EMAC_RMR_ARP		(0x10000000)
+#define EMAC_RMR_AROP		(0x08000000)
+#define EMAC_RMR_ARPI		(0x04000000)
+#define EMAC_RMR_PPP		(0x02000000)
+#define EMAC_RMR_PME		(0x01000000)
+#define EMAC_RMR_PMME		(0x00800000)
+#define EMAC_RMR_IAE		(0x00400000)
+#define EMAC_RMR_MIAE		(0x00200000)
+#define EMAC_RMR_BAE		(0x00100000)
+#define EMAC_RMR_MAE		(0x00080000)
+
+/* Interrupt Status & enable Regs */
+#define EMAC_ISR_OVR		(0x02000000)
+#define EMAC_ISR_PP		(0x01000000)
+#define EMAC_ISR_BP		(0x00800000)
+#define EMAC_ISR_RP		(0x00400000)
+#define EMAC_ISR_SE		(0x00200000)
+#define EMAC_ISR_SYE		(0x00100000)
+#define EMAC_ISR_BFCS		(0x00080000)
+#define EMAC_ISR_PTLE		(0x00040000)
+#define EMAC_ISR_ORE		(0x00020000)
+#define EMAC_ISR_IRE		(0x00010000)
+#define EMAC_ISR_DBDM		(0x00000200)
+#define EMAC_ISR_DB0		(0x00000100)
+#define EMAC_ISR_SE0		(0x00000080)
+#define EMAC_ISR_TE0		(0x00000040)
+#define EMAC_ISR_DB1		(0x00000020)
+#define EMAC_ISR_SE1		(0x00000010)
+#define EMAC_ISR_TE1		(0x00000008)
+#define EMAC_ISR_MOS		(0x00000002)
+#define EMAC_ISR_MOF		(0x00000001)
+
+/* STA CONTROL REG */
+#define EMAC_STACR_OC		(0x00008000)
+#define EMAC_STACR_PHYE		(0x00004000)
+
+#ifdef CONFIG_IBM_EMAC4_V4	/* EMAC4 V4 changed bit setting */
+#define EMAC_STACR_INDIRECT_MODE (0x00002000)
+#define EMAC_STACR_WRITE	(0x00000800) /* $BUC */
+#define EMAC_STACR_READ		(0x00001000) /* $BUC */
+#define EMAC_STACR_OP_MASK	(0x00001800)
+#define EMAC_STACR_MDIO_ADDR	(0x00000000)
+#define EMAC_STACR_MDIO_WRITE	(0x00000800)
+#define EMAC_STACR_MDIO_READ	(0x00001800)
+#define EMAC_STACR_MDIO_READ_INC (0x00001000)
+#else
+#define EMAC_STACR_WRITE	(0x00002000)
+#define EMAC_STACR_READ		(0x00001000)
+#endif
+
+#define EMAC_STACR_CLK_83MHZ	(0x00000800)  /* 0's for 50Mhz */
+#define EMAC_STACR_CLK_66MHZ	(0x00000400)
+#define EMAC_STACR_CLK_100MHZ	(0x00000C00)
+
+/* Transmit Request Threshold Register */
+#define EMAC_TRTR_256		(0x18000000)   /* 0's for 64 Bytes */
+#define EMAC_TRTR_192		(0x10000000)
+#define EMAC_TRTR_128		(0x01000000)
+
+/* the follwing defines are for the MadMAL status and control registers. */
+/* For bits 0..5 look at the mal.h file					 */
+#define EMAC_TX_CTRL_GFCS	(0x0200)
+#define EMAC_TX_CTRL_GP		(0x0100)
+#define EMAC_TX_CTRL_ISA	(0x0080)
+#define EMAC_TX_CTRL_RSA	(0x0040)
+#define EMAC_TX_CTRL_IVT	(0x0020)
+#define EMAC_TX_CTRL_RVT	(0x0010)
+
+#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
+
+#define EMAC_TX_ST_BFCS		(0x0200)
+#define EMAC_TX_ST_BPP		(0x0100)
+#define EMAC_TX_ST_LCS		(0x0080)
+#define EMAC_TX_ST_ED		(0x0040)
+#define EMAC_TX_ST_EC		(0x0020)
+#define EMAC_TX_ST_LC		(0x0010)
+#define EMAC_TX_ST_MC		(0x0008)
+#define EMAC_TX_ST_SC		(0x0004)
+#define EMAC_TX_ST_UR		(0x0002)
+#define EMAC_TX_ST_SQE		(0x0001)
+
+#define EMAC_TX_ST_DEFAULT	(0x03F3)
+
+
+/* madmal receive status / Control bits */
+
+#define EMAC_RX_ST_OE		(0x0200)
+#define EMAC_RX_ST_PP		(0x0100)
+#define EMAC_RX_ST_BP		(0x0080)
+#define EMAC_RX_ST_RP		(0x0040)
+#define EMAC_RX_ST_SE		(0x0020)
+#define EMAC_RX_ST_AE		(0x0010)
+#define EMAC_RX_ST_BFCS		(0x0008)
+#define EMAC_RX_ST_PTL		(0x0004)
+#define EMAC_RX_ST_ORE		(0x0002)
+#define EMAC_RX_ST_IRE		(0x0001)
+/* all the errors we care about */
+#define EMAC_RX_ERRORS		(0x03FF)
+
+#endif /* _PPC4XX_ENET_H_ */
diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/ppc4xx-gpio.h
index 23e29b1..23e29b1 100644
--- a/arch/powerpc/include/asm/gpio.h
+++ b/arch/powerpc/include/asm/ppc4xx-gpio.h
diff --git a/arch/powerpc/include/asm/ppc4xx-i2c.h b/arch/powerpc/include/asm/ppc4xx-i2c.h
new file mode 100644
index 0000000..0c6c926
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc4xx-i2c.h
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2007-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _4xx_i2c_h_
+#define _4xx_i2c_h_
+
+#define IIC_OK		0
+#define IIC_NOK		1
+#define IIC_NOK_LA	2		/* Lost arbitration */
+#define IIC_NOK_ICT	3		/* Incomplete transfer */
+#define IIC_NOK_XFRA	4		/* Transfer aborted */
+#define IIC_NOK_DATA	5		/* No data in buffer */
+#define IIC_NOK_TOUT	6		/* Transfer timeout */
+
+#define IIC_TIMEOUT	1		/* 1 second */
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+#define I2C_BUS_OFFS	(i2c_bus_num * 0x100)
+#else
+#define I2C_BUS_OFFS	(0x000)
+#endif /* CONFIG_I2C_MULTI_BUS */
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define I2C_BASE_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
+#elif defined(CONFIG_440) || defined(CONFIG_405EX)
+/* all remaining 440 variants */
+#define I2C_BASE_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
+#else
+/* all 405 variants */
+#define I2C_BASE_ADDR	(0xEF600500 + I2C_BUS_OFFS)
+#endif
+
+struct ppc4xx_i2c {
+	u8 mdbuf;
+	u8 res1;
+	u8 sdbuf;
+	u8 res2;
+	u8 lmadr;
+	u8 hmadr;
+	u8 cntl;
+	u8 mdcntl;
+	u8 sts;
+	u8 extsts;
+	u8 lsadr;
+	u8 hsadr;
+	u8 clkdiv;
+	u8 intrmsk;
+	u8 xfrcnt;
+	u8 xtcntlss;
+	u8 directcntl;
+	u8 intr;
+};
+
+/* MDCNTL Register Bit definition */
+#define IIC_MDCNTL_HSCL		0x01
+#define IIC_MDCNTL_EUBS		0x02
+#define IIC_MDCNTL_EINT		0x04
+#define IIC_MDCNTL_ESM		0x08
+#define IIC_MDCNTL_FSM		0x10
+#define IIC_MDCNTL_EGC		0x20
+#define IIC_MDCNTL_FMDB		0x40
+#define IIC_MDCNTL_FSDB		0x80
+
+/* CNTL Register Bit definition */
+#define IIC_CNTL_PT		0x01
+#define IIC_CNTL_READ		0x02
+#define IIC_CNTL_CHT		0x04
+#define IIC_CNTL_RPST		0x08
+/* bit 2/3 for Transfer count*/
+#define IIC_CNTL_AMD		0x40
+#define IIC_CNTL_HMT		0x80
+
+/* STS Register Bit definition */
+#define IIC_STS_PT		0x01
+#define IIC_STS_IRQA		0x02
+#define IIC_STS_ERR		0x04
+#define IIC_STS_SCMP		0x08
+#define IIC_STS_MDBF		0x10
+#define IIC_STS_MDBS		0x20
+#define IIC_STS_SLPR		0x40
+#define IIC_STS_SSS		0x80
+
+/* EXTSTS Register Bit definition */
+#define IIC_EXTSTS_XFRA		0x01
+#define IIC_EXTSTS_ICT		0x02
+#define IIC_EXTSTS_LA		0x04
+
+/* XTCNTLSS Register Bit definition */
+#define IIC_XTCNTLSS_SRST	0x01
+#define IIC_XTCNTLSS_EPI	0x02
+#define IIC_XTCNTLSS_SDBF	0x04
+#define IIC_XTCNTLSS_SBDD	0x08
+#define IIC_XTCNTLSS_SWS	0x10
+#define IIC_XTCNTLSS_SWC	0x20
+#define IIC_XTCNTLSS_SRS	0x40
+#define IIC_XTCNTLSS_SRC	0x80
+
+/* IICx_DIRECTCNTL register */
+#define IIC_DIRCNTL_SDAC	0x08
+#define IIC_DIRCNTL_SCC		0x04
+#define IIC_DIRCNTL_MSDA	0x02
+#define IIC_DIRCNTL_MSC		0x01
+
+#define DIRCTNL_FREE(v)		(((v) & 0x0f) == 0x0f)
+#endif
diff --git a/arch/powerpc/include/asm/ppc4xx-mal.h b/arch/powerpc/include/asm/ppc4xx-mal.h
new file mode 100644
index 0000000..7198685
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc4xx-mal.h
@@ -0,0 +1,168 @@
+/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
+/*----------------------------------------------------------------------------+
+|   This source code is dual-licensed.  You may use it under the terms of the
+|   GNU General Public License version 2, or under the license below.
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|
+|  File Name:	mal.h
+|
+|  Function:	Header file for the MAL (MADMAL) macro on the 405GP.
+|
+|  Author:	Mark Wisner
+|
+|  Change Activity-
+|
+|  Date	       Description of Change					   BY
+|  ---------   ---------------------					   ---
+|  29-Apr-99   Created							   MKW
+|
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|  17-Nov-03  Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+|	      Added register bit definitions to support multiple channels
++----------------------------------------------------------------------------*/
+#ifndef _mal_h_
+#define _mal_h_
+
+#if !defined(MAL_DCR_BASE)
+#define MAL_DCR_BASE	0x180
+#endif
+#define MAL0_CFG	(MAL_DCR_BASE + 0x00)	/* MAL Config reg	*/
+#define MAL0_ESR	(MAL_DCR_BASE + 0x01)	/* Error Status (Read/Clear) */
+#define MAL0_IER	(MAL_DCR_BASE + 0x02)	/* Interrupt enable */
+#define MAL0_TXCASR	(MAL_DCR_BASE + 0x04)	/* TX Channel active (set) */
+#define MAL0_TXCARR	(MAL_DCR_BASE + 0x05)	/* TX Channel active (reset) */
+#define MAL0_TXEOBISR	(MAL_DCR_BASE + 0x06)	/* TX End of buffer int status*/
+#define MAL0_TXDEIR	(MAL_DCR_BASE + 0x07)	/* TX Descr. Error Int */
+#define MAL0_TXBADDR	(MAL_DCR_BASE + 0x09)	/* TX descriptor base addr*/
+#define MAL0_RXCASR	(MAL_DCR_BASE + 0x10)	/* RX Channel active (set) */
+#define MAL0_RXCARR	(MAL_DCR_BASE + 0x11)	/* RX Channel active (reset) */
+#define MAL0_RXEOBISR	(MAL_DCR_BASE + 0x12)	/* RX End of buffer int status*/
+#define MAL0_RXDEIR	(MAL_DCR_BASE + 0x13)	/* RX Descr. Error Int */
+#define MAL0_RXBADDR	(MAL_DCR_BASE + 0x15)	/* RX descriptor base addr */
+#define MAL0_TXCTP0R	(MAL_DCR_BASE + 0x20)	/* TX 0 Channel table pointer */
+#define MAL0_TXCTP1R	(MAL_DCR_BASE + 0x21)	/* TX 1 Channel table pointer */
+#define MAL0_TXCTP2R	(MAL_DCR_BASE + 0x22)	/* TX 2 Channel table pointer */
+#define MAL0_TXCTP3R	(MAL_DCR_BASE + 0x23)	/* TX 3 Channel table pointer */
+#define MAL0_RXCTP0R	(MAL_DCR_BASE + 0x40)	/* RX 0 Channel table pointer */
+#define MAL0_RXCTP1R	(MAL_DCR_BASE + 0x41)	/* RX 1 Channel table pointer */
+#define MAL0_RCBS0	(MAL_DCR_BASE + 0x60)	/* RX 0 Channel buffer size */
+#define MAL0_RCBS1	(MAL_DCR_BASE + 0x61)	/* RX 1 Channel buffer size */
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define MAL0_RXCTP2R	(MAL_DCR_BASE + 0x42)	/* RX 2 Channel table pointer */
+#define MAL0_RXCTP3R	(MAL_DCR_BASE + 0x43)	/* RX 3 Channel table pointer */
+#define MAL0_RXCTP8R	(MAL_DCR_BASE + 0x48)	/* RX 8 Channel table pointer */
+#define MAL0_RXCTP16R	(MAL_DCR_BASE + 0x50)	/* RX 16 Channel table pointer*/
+#define MAL0_RXCTP24R	(MAL_DCR_BASE + 0x58)	/* RX 24 Channel table pointer*/
+#define MAL0_RCBS2	(MAL_DCR_BASE + 0x62)	/* RX 2 Channel buffer size */
+#define MAL0_RCBS3	(MAL_DCR_BASE + 0x63)	/* RX 3 Channel buffer size */
+#define MAL0_RCBS8	(MAL_DCR_BASE + 0x68)	/* RX 8 Channel buffer size */
+#define MAL0_RCBS16	(MAL_DCR_BASE + 0x70)	/* RX 16 Channel buffer size */
+#define MAL0_RCBS24	(MAL_DCR_BASE + 0x78)	/* RX 24 Channel buffer size */
+#endif /* CONFIG_440GX */
+
+/* MADMAL transmit and receive status/control bits  */
+/* for COMMAC bits, refer to the COMMAC header file */
+
+#define MAL_TX_CTRL_READY 0x8000
+#define MAL_TX_CTRL_WRAP  0x4000
+#define MAL_TX_CTRL_CM	  0x2000
+#define MAL_TX_CTRL_LAST  0x1000
+#define MAL_TX_CTRL_INTR  0x0400
+
+#define MAL_RX_CTRL_EMPTY 0x8000
+#define MAL_RX_CTRL_WRAP  0x4000
+#define MAL_RX_CTRL_CM	  0x2000
+#define MAL_RX_CTRL_LAST  0x1000
+#define MAL_RX_CTRL_FIRST 0x0800
+#define MAL_RX_CTRL_INTR  0x0400
+
+      /* Configuration Reg  */
+#define MAL_CR_MMSR	  0x80000000
+#define MAL_CR_PLBP_1	  0x00400000   /* lowsest is 00 */
+#define MAL_CR_PLBP_2	  0x00800000
+#define MAL_CR_PLBP_3	  0x00C00000   /* highest	*/
+#define MAL_CR_GA	  0x00200000
+#define MAL_CR_OA	  0x00100000
+#define MAL_CR_PLBLE	  0x00080000
+#define MAL_CR_PLBLT_1	0x00040000
+#define MAL_CR_PLBLT_2	0x00020000
+#define MAL_CR_PLBLT_3	0x00010000
+#define MAL_CR_PLBLT_4	0x00008000
+#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
+#define MAL_CR_PLBB	  0x00004000
+#define MAL_CR_OPBBL	  0x00000080
+#define MAL_CR_EOPIE	  0x00000004
+#define MAL_CR_LEA	  0x00000002
+#define MAL_CR_MSD	  0x00000001
+
+    /* Error Status Reg	   */
+#define MAL_ESR_EVB	  0x80000000
+#define MAL_ESR_CID	  0x40000000
+#define MAL_ESR_DE	  0x00100000
+#define MAL_ESR_ONE	  0x00080000
+#define MAL_ESR_OTE	  0x00040000
+#define MAL_ESR_OSE	  0x00020000
+#define MAL_ESR_PEIN	  0x00010000
+      /* same bit position as the IER */
+      /* VV			 VV   */
+#define MAL_ESR_DEI	  0x00000010
+#define MAL_ESR_ONEI	  0x00000008
+#define MAL_ESR_OTEI	  0x00000004
+#define MAL_ESR_OSEI	  0x00000002
+#define MAL_ESR_PBEI	  0x00000001
+      /* ^^			 ^^   */
+      /* Mal IER		      */
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+#define MAL_IER_PT	  0x00000080
+#define MAL_IER_PRE	  0x00000040
+#define MAL_IER_PWE	  0x00000020
+#define MAL_IER_DE	  0x00000010
+#define MAL_IER_OTE	  0x00000004
+#define MAL_IER_OE	  0x00000002
+#define MAL_IER_PE	  0x00000001
+#else
+#define MAL_IER_DE	  0x00000010
+#define MAL_IER_NE	  0x00000008
+#define MAL_IER_TE	  0x00000004
+#define MAL_IER_OPBE	  0x00000002
+#define MAL_IER_PLBE	  0x00000001
+#endif
+
+/* MAL Channel Active Set and Reset Registers */
+#define MAL_TXRX_CASR	(0x80000000)
+
+#define MAL_TXRX_CASR_V(__x)  (__x)  /* Channel 0 shifts 0, channel 1 shifts 1, etc */
+
+
+/* MAL Buffer Descriptor structure */
+typedef struct {
+  short	 ctrl;		    /* MAL / Commac status control bits */
+  short	 data_len;	    /* Max length is 4K-1 (12 bits)	*/
+  char	*data_ptr;	    /* pointer to actual data buffer	*/
+} mal_desc_t;
+
+#endif
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 4ec1ef8..ac150c2 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -951,8 +951,6 @@
 #define SDRAM_RTSR_TRK1SM_ATPLS1	0x80000000	/* atpls1 state		*/
 #define SDRAM_RTSR_TRK1SM_RESET		0xC0000000	/* reset  state		*/
 
-#define SDR0_MFR_FIXD			0x10000000	/* Workaround for PCI/DMA */
-
 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
 
 #if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h
new file mode 100644
index 0000000..87a16ec
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc4xx.h
@@ -0,0 +1,344 @@
+/*----------------------------------------------------------------------------+
+|       This source code is dual-licensed.  You may use it under the terms of
+|       the GNU General Public License version 2, or under the license below.
+|
+|       This source code has been made available to you by IBM on an AS-IS
+|       basis.  Anyone receiving this source is licensed under IBM
+|       copyrights to use it in any way he or she deems fit, including
+|       copying it, modifying it, compiling it, and redistributing it either
+|       with or without modifications.  No license under IBM patents or
+|       patent applications is to be implied by the copyright license.
+|
+|       Any user of this software should understand that IBM cannot provide
+|       technical support for this software and will not be responsible for
+|       any consequences resulting from the use of this software.
+|
+|       Any person who transfers this source code or any derivative work
+|       must include the IBM copyright notice, this paragraph, and the
+|       preceding two paragraphs in the transferred software.
+|
+|       COPYRIGHT   I B M   CORPORATION 1999
+|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+#ifndef	__PPC4XX_H__
+#define __PPC4XX_H__
+
+/*
+ * Include SoC specific headers
+ */
+#if defined(CONFIG_405CR)
+#include <asm/ppc405cr.h>
+#endif
+
+#if defined(CONFIG_405EP)
+#include <asm/ppc405ep.h>
+#endif
+
+#if defined(CONFIG_405EX)
+#include <asm/ppc405ex.h>
+#endif
+
+#if defined(CONFIG_405EZ)
+#include <asm/ppc405ez.h>
+#endif
+
+#if defined(CONFIG_405GP)
+#include <asm/ppc405gp.h>
+#endif
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#include <asm/ppc440ep_gr.h>
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#include <asm/ppc440epx_grx.h>
+#endif
+
+#if defined(CONFIG_440GP)
+#include <asm/ppc440gp.h>
+#endif
+
+#if defined(CONFIG_440GX)
+#include <asm/ppc440gx.h>
+#endif
+
+#if defined(CONFIG_440SP)
+#include <asm/ppc440sp.h>
+#endif
+
+#if defined(CONFIG_440SPE)
+#include <asm/ppc440spe.h>
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#include <asm/ppc460ex_gt.h>
+#endif
+
+#if defined(CONFIG_460SX)
+#include <asm/ppc460sx.h>
+#endif
+
+/*
+ * Configure which SDRAM/DDR/DDR2 controller is equipped
+ */
+// test-only: what to do with these???
+#if defined(CONFIG_AP1000) || defined(CONFIG_ML2)
+#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM	/* IBM SDRAM controller */
+#endif
+
+/*
+ * Common registers for all SoC's
+ */
+/* DCR registers */
+#define PLB3A0_ACR	0x0077
+#define PLB4A0_ACR	0x0081
+#define PLB4A1_ACR	0x0089
+
+/* CPR register declarations */
+
+#define PLB4Ax_ACR_PPM_MASK		0xf0000000
+#define PLB4Ax_ACR_PPM_FIXED		0x00000000
+#define PLB4Ax_ACR_PPM_FAIR		0xd0000000
+#define PLB4Ax_ACR_HBU_MASK		0x08000000
+#define PLB4Ax_ACR_HBU_DISABLED		0x00000000
+#define PLB4Ax_ACR_HBU_ENABLED		0x08000000
+#define PLB4Ax_ACR_RDP_MASK		0x06000000
+#define PLB4Ax_ACR_RDP_DISABLED		0x00000000
+#define PLB4Ax_ACR_RDP_2DEEP		0x02000000
+#define PLB4Ax_ACR_RDP_3DEEP		0x04000000
+#define PLB4Ax_ACR_RDP_4DEEP		0x06000000
+#define PLB4Ax_ACR_WRP_MASK		0x01000000
+#define PLB4Ax_ACR_WRP_DISABLED		0x00000000
+#define PLB4Ax_ACR_WRP_2DEEP		0x01000000
+
+/*
+ * External Bus Controller
+ */
+/* Values for EBC0_CFGADDR register - indirect addressing of these regs */
+#define PB0CR		0x00	/* periph bank 0 config reg		*/
+#define PB1CR		0x01	/* periph bank 1 config reg		*/
+#define PB2CR		0x02	/* periph bank 2 config reg		*/
+#define PB3CR		0x03	/* periph bank 3 config reg		*/
+#define PB4CR		0x04	/* periph bank 4 config reg		*/
+#define PB5CR		0x05	/* periph bank 5 config reg		*/
+#define PB6CR		0x06	/* periph bank 6 config reg		*/
+#define PB7CR		0x07	/* periph bank 7 config reg		*/
+#define PB0AP		0x10	/* periph bank 0 access parameters	*/
+#define PB1AP		0x11	/* periph bank 1 access parameters	*/
+#define PB2AP		0x12	/* periph bank 2 access parameters	*/
+#define PB3AP		0x13	/* periph bank 3 access parameters	*/
+#define PB4AP		0x14	/* periph bank 4 access parameters	*/
+#define PB5AP		0x15	/* periph bank 5 access parameters	*/
+#define PB6AP		0x16	/* periph bank 6 access parameters	*/
+#define PB7AP		0x17	/* periph bank 7 access parameters	*/
+#define PBEAR		0x20	/* periph bus error addr reg		*/
+#define PBESR0		0x21	/* periph bus error status reg 0	*/
+#define PBESR1		0x22	/* periph bus error status reg 1	*/
+#define EBC0_CFG	0x23	/* external bus configuration reg	*/
+
+/*
+ * GPIO macro register defines
+ */
+/* todo: merge with gpio.h header */
+#define GPIO_BASE		GPIO0_BASE
+
+#define GPIO0_OR		(GPIO0_BASE + 0x0)
+#define GPIO0_TCR		(GPIO0_BASE + 0x4)
+#define GPIO0_OSRL		(GPIO0_BASE + 0x8)
+#define GPIO0_OSRH		(GPIO0_BASE + 0xC)
+#define GPIO0_TSRL		(GPIO0_BASE + 0x10)
+#define GPIO0_TSRH		(GPIO0_BASE + 0x14)
+#define GPIO0_ODR		(GPIO0_BASE + 0x18)
+#define GPIO0_IR		(GPIO0_BASE + 0x1C)
+#define GPIO0_RR1		(GPIO0_BASE + 0x20)
+#define GPIO0_RR2		(GPIO0_BASE + 0x24)
+#define GPIO0_RR3		(GPIO0_BASE + 0x28)
+#define GPIO0_ISR1L		(GPIO0_BASE + 0x30)
+#define GPIO0_ISR1H		(GPIO0_BASE + 0x34)
+#define GPIO0_ISR2L		(GPIO0_BASE + 0x38)
+#define GPIO0_ISR2H		(GPIO0_BASE + 0x3C)
+#define GPIO0_ISR3L		(GPIO0_BASE + 0x40)
+#define GPIO0_ISR3H		(GPIO0_BASE + 0x44)
+
+#define GPIO1_OR		(GPIO1_BASE + 0x0)
+#define GPIO1_TCR		(GPIO1_BASE + 0x4)
+#define GPIO1_OSRL		(GPIO1_BASE + 0x8)
+#define GPIO1_OSRH		(GPIO1_BASE + 0xC)
+#define GPIO1_TSRL		(GPIO1_BASE + 0x10)
+#define GPIO1_TSRH		(GPIO1_BASE + 0x14)
+#define GPIO1_ODR		(GPIO1_BASE + 0x18)
+#define GPIO1_IR		(GPIO1_BASE + 0x1C)
+#define GPIO1_RR1		(GPIO1_BASE + 0x20)
+#define GPIO1_RR2		(GPIO1_BASE + 0x24)
+#define GPIO1_RR3		(GPIO1_BASE + 0x28)
+#define GPIO1_ISR1L		(GPIO1_BASE + 0x30)
+#define GPIO1_ISR1H		(GPIO1_BASE + 0x34)
+#define GPIO1_ISR2L		(GPIO1_BASE + 0x38)
+#define GPIO1_ISR2H		(GPIO1_BASE + 0x3C)
+#define GPIO1_ISR3L		(GPIO1_BASE + 0x40)
+#define GPIO1_ISR3H		(GPIO1_BASE + 0x44)
+
+/* General Purpose Timer (GPT) Register Offsets */
+#define GPT0_TBC		0x00000000
+#define GPT0_IM			0x00000018
+#define GPT0_ISS		0x0000001C
+#define GPT0_ISC		0x00000020
+#define GPT0_IE			0x00000024
+#define GPT0_COMP0		0x00000080
+#define GPT0_COMP1		0x00000084
+#define GPT0_COMP2		0x00000088
+#define GPT0_COMP3		0x0000008C
+#define GPT0_COMP4		0x00000090
+#define GPT0_COMP5		0x00000094
+#define GPT0_COMP6		0x00000098
+#define GPT0_MASK0		0x000000C0
+#define GPT0_MASK1		0x000000C4
+#define GPT0_MASK2		0x000000C8
+#define GPT0_MASK3		0x000000CC
+#define GPT0_MASK4		0x000000D0
+#define GPT0_MASK5		0x000000D4
+#define GPT0_MASK6		0x000000D8
+#define GPT0_DCT0		0x00000110
+#define GPT0_DCIS		0x0000011C
+
+#if 0 // test-only
+/*
+ * All PPC4xx share the same NS16550 UART(s). Only base addresses
+ * may differ. We define here the integration of the common NS16550
+ * driver for all PPC4xx SoC's. The board config header must specify
+ * on which UART the console should be located via CONFIG_CONS_INDEX.
+ */
+#if 0 /* test-only */
+#define CONFIG_SERIAL_MULTI
+#endif
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#endif
+
+#if defined(CONFIG_440)
+#include <asm/ppc440.h>
+#else
+#include <asm/ppc405.h>
+#endif
+
+#include <asm/ppc4xx-sdram.h>
+#include <asm/ppc4xx-ebc.h>
+#if !defined(CONFIG_XILINX_440)
+#include <asm/ppc4xx-uic.h>
+#endif
+
+/*
+ * Macro for generating register field mnemonics
+ */
+#define	PPC_REG_BITS		32
+#define	PPC_REG_VAL(bit, value)	((value) << ((PPC_REG_BITS - 1) - (bit)))
+
+/*
+ * Elide casts when assembling register mnemonics
+ */
+#ifndef __ASSEMBLY__
+#define	static_cast(type, val)	(type)(val)
+#else
+#define	static_cast(type, val)	(val)
+#endif
+
+/*
+ * Common stuff for 4xx (405 and 440)
+ */
+
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset			*/
+#define _START_OFFSET		(EXC_OFF_SYS_RESET + 0x2000)
+
+#define RESET_VECTOR	0xfffffffc
+#define CACHELINE_MASK	(CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
+						cache line aligned data. */
+
+#define CPR0_DCR_BASE	0x0C
+#define CPR0_CFGADDR	(CPR0_DCR_BASE + 0x0)
+#define CPR0_CFGDATA	(CPR0_DCR_BASE + 0x1)
+
+#define SDR_DCR_BASE	0x0E
+#define SDR0_CFGADDR	(SDR_DCR_BASE + 0x0)
+#define SDR0_CFGDATA	(SDR_DCR_BASE + 0x1)
+
+#define SDRAM_DCR_BASE	0x10
+#define SDRAM0_CFGADDR	(SDRAM_DCR_BASE + 0x0)
+#define SDRAM0_CFGDATA	(SDRAM_DCR_BASE + 0x1)
+
+#define EBC_DCR_BASE	0x12
+#define EBC0_CFGADDR	(EBC_DCR_BASE + 0x0)
+#define EBC0_CFGDATA	(EBC_DCR_BASE + 0x1)
+
+/*
+ * Macros for indirect DCR access
+ */
+#define mtcpr(reg, d)	\
+  do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
+#define mfcpr(reg, d)	\
+  do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
+
+#define mtebc(reg, d)	\
+  do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
+#define mfebc(reg, d)	\
+  do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
+
+#define mtsdram(reg, d)	\
+  do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
+#define mfsdram(reg, d)	\
+  do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
+
+#define mtsdr(reg, d)	\
+  do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
+#define mfsdr(reg, d)	\
+  do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+	unsigned long freqDDR;
+	unsigned long freqEBC;
+	unsigned long freqOPB;
+	unsigned long freqPCI;
+	unsigned long freqPLB;
+	unsigned long freqTmrClk;
+	unsigned long freqUART;
+	unsigned long freqProcessor;
+	unsigned long freqVCOHz;
+	unsigned long freqVCOMhz;	/* in MHz                          */
+	unsigned long pciClkSync;	/* PCI clock is synchronous        */
+	unsigned long pciIntArbEn;	/* Internal PCI arbiter is enabled */
+	unsigned long pllExtBusDiv;
+	unsigned long pllFbkDiv;
+	unsigned long pllFwdDiv;
+	unsigned long pllFwdDivA;
+	unsigned long pllFwdDivB;
+	unsigned long pllOpbDiv;
+	unsigned long pllPciDiv;
+	unsigned long pllPlbDiv;
+} PPC4xx_SYS_INFO;
+
+static inline u32 get_mcsr(void)
+{
+	u32 val;
+
+	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+	return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
+int ppc4xx_pci_sync_clock_config(u32 async);
+
+#endif	/* __ASSEMBLY__ */
+
+/* for multi-cpu support */
+#define NA_OR_UNKNOWN_CPU	-1
+
+#endif	/* __PPC4XX_H__ */
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 628d067..8f6a7c9 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -118,16 +118,6 @@ extern int board_start_ide(void);
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_ENV_IS_EMBEDDED)
-#define TOTAL_MALLOC_LEN	CONFIG_SYS_MALLOC_LEN
-#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
-	(CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
-      defined(CONFIG_ENV_IS_IN_NVRAM)
-#define	TOTAL_MALLOC_LEN	(CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
-#else
-#define	TOTAL_MALLOC_LEN	CONFIG_SYS_MALLOC_LEN
-#endif
-
 #if !defined(CONFIG_SYS_MEM_TOP_HIDE)
 #define CONFIG_SYS_MEM_TOP_HIDE	0
 #endif
@@ -519,15 +509,12 @@ void board_init_f (ulong bootflag)
 	bd->bi_memstart  = CONFIG_SYS_SDRAM_BASE;	/* start of  DRAM memory	*/
 	bd->bi_memsize   = gd->ram_size;	/* size  of  DRAM memory in bytes */
 
-#ifdef CONFIG_IP860
-	bd->bi_sramstart = SRAM_BASE;	/* start of  SRAM memory	*/
-	bd->bi_sramsize  = SRAM_SIZE;	/* size  of  SRAM memory	*/
-#elif defined CONFIG_MPC8220
+#ifdef CONFIG_SYS_SRAM_BASE
 	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;	/* start of  SRAM memory	*/
 	bd->bi_sramsize  = CONFIG_SYS_SRAM_SIZE;	/* size  of  SRAM memory	*/
 #else
-	bd->bi_sramstart = 0;		/* FIXME */ /* start of  SRAM memory	*/
-	bd->bi_sramsize  = 0;		/* FIXME */ /* size  of  SRAM memory	*/
+	bd->bi_sramstart = 0;
+	bd->bi_sramsize  = 0;
 #endif
 
 #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
@@ -914,13 +901,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	 */
 	interrupt_init ();
 
-	/* Must happen after interrupts are initialized since
-	 * an irq handler gets installed
-	 */
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
-	serial_buffered_init();
-#endif
-
 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
 	status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
 #endif