diff options
| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2014-04-24 11:10:09 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-05-13 08:26:54 -0700 |
| commit | c665c473b605349b1c58890493255dd70e0b60fe (patch) | |
| tree | a3ef31df4029707bfc0f1f51d8319b2cea284a58 /arch/powerpc | |
| parent | 3a7ed5aa232da1d2836b5d3962e59e685307122e (diff) | |
| download | u-boot-imx-c665c473b605349b1c58890493255dd70e0b60fe.zip u-boot-imx-c665c473b605349b1c58890493255dd70e0b60fe.tar.gz u-boot-imx-c665c473b605349b1c58890493255dd70e0b60fe.tar.bz2 | |
powerpc/t208x: enable errata A006261, A006593, A006379
Enable errata A006261, A006593, A006379 for T208x.
Additionally enable CONFIG_CMD_ERRATA for T2080RDB.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 3 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_errata.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 864e74c..0d6eb49 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -798,6 +798,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 4eba85c..d820121 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -52,6 +52,9 @@ static inline bool has_erratum_a006261(void) return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T1040: return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0); case SVR_P5040: return IS_SVR_REV(svr, 1, 0); } |