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| author | Stefan Roese <sr@denx.de> | 2010-05-25 15:33:14 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-07-01 10:26:15 +0200 |
| commit | e9c020df9608c58ccd35a000bceadbb91ffe5f23 (patch) | |
| tree | b55fcd1f487fa9bb26500411a3bfb48a13f3b468 /arch/powerpc | |
| parent | 066003b2c5540bde3c29ac6f8a4fbde24dd0b2f0 (diff) | |
| download | u-boot-imx-e9c020df9608c58ccd35a000bceadbb91ffe5f23.zip u-boot-imx-e9c020df9608c58ccd35a000bceadbb91ffe5f23.tar.gz u-boot-imx-e9c020df9608c58ccd35a000bceadbb91ffe5f23.tar.bz2 | |
ppc4xx: DDR2: Complete RDSS configuration on non-SPD based boards
As described in item #10 of the SDRAM initialization (chapter 22.2.9
of the PPC460EX/EXr/GT users manual), RDSS may need to be adjusted. The
code for this is now factored out and executed for non-SPD based boards
as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 52 |
1 files changed, 38 insertions, 14 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index faddee9..b2cc2fe 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -68,6 +68,31 @@ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ } while (0) +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +static void update_rdcc(void) +{ + u32 val; + + /* + * Complete RDSS configuration as mentioned on page 7 of the AMCC + * PowerPC440SP/SPe DDR2 application note: + * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" + * + * Or item #10 "10. Complete RDSS configuration" in chapter + * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users + * manual. + */ + mfsdram(SDRAM_RTSR, val); + if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) { + mfsdram(SDRAM_RDCC, val); + if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) { + val += 0x40000000; + mtsdram(SDRAM_RDCC, val); + } + } +} +#endif + #if defined(CONFIG_440) /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 @@ -620,6 +645,12 @@ phys_size_t initdram(int board_type) #else program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks); #endif + /* + * Now complete RDSS configuration as mentioned on page 7 of the AMCC + * PowerPC440SP/SPe DDR2 application note: + * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" + */ + update_rdcc(); #ifdef CONFIG_DDR_ECC /*------------------------------------------------------------------ @@ -2692,20 +2723,6 @@ calibration_loop: blank_string(strlen(str)); #endif /* CONFIG_DDR_RQDC_FIXED */ - /* - * Now complete RDSS configuration as mentioned on page 7 of the AMCC - * PowerPC440SP/SPe DDR2 application note: - * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" - */ - mfsdram(SDRAM_RTSR, val); - if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) { - mfsdram(SDRAM_RDCC, val); - if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) { - val += 0x40000000; - mtsdram(SDRAM_RDCC, val); - } - } - mfsdram(SDRAM_DLCR, val); debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val); mfsdram(SDRAM_RQDC, val); @@ -3007,6 +3024,13 @@ phys_size_t initdram(int board_type) #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ + /* + * Now complete RDSS configuration as mentioned on page 7 of the AMCC + * PowerPC440SP/SPe DDR2 application note: + * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" + */ + update_rdcc(); + #if defined(CONFIG_DDR_ECC) do_program_ecc(0); #endif /* defined(CONFIG_DDR_ECC) */ |