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| author | Kumar Gala <galak@kernel.crashing.org> | 2011-01-29 15:36:10 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-02-03 02:46:12 -0600 |
| commit | 5103a03a0be2fd1a5270046d9f2bc77916e33a56 (patch) | |
| tree | 969486ff9a138e255386e4767525027454235448 /arch/powerpc | |
| parent | 6e7f0bc0ce33adbd028f4e34b7e9d3bf46e0f95b (diff) | |
| download | u-boot-imx-5103a03a0be2fd1a5270046d9f2bc77916e33a56.zip u-boot-imx-5103a03a0be2fd1a5270046d9f2bc77916e33a56.tar.gz u-boot-imx-5103a03a0be2fd1a5270046d9f2bc77916e33a56.tar.bz2 | |
fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)
Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8,
and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 0cc8b1e..4f8134b 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -59,6 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136) puts("Work-around for Erratum ESDHC136 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) + puts("Work-around for Erratum ESDHC-A001 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 puts("Work-around for Erratum CPC-A002 enabled\n"); #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 9919d97..c771a4b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -131,12 +131,14 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 #elif defined(CONFIG_P2020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 #elif defined(CONFIG_PPC_P2040) #define CONFIG_MAX_CPUS 4 |