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authormario.six@gdsys.cc <mario.six@gdsys.cc>2016-05-25 15:15:20 +0200
committerYork Sun <york.sun@nxp.com>2016-06-03 22:13:24 -0700
commit07d31f8f98fb350776c78a681ef27fd8ee288acd (patch)
tree724a919f480470a53e8cd03c42561a19e3844172 /arch/powerpc
parentb7707b043ebbf88fe0fb49442db9316ded3a0740 (diff)
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dm: gpio: Add driver for MPC85XX GPIO controller
This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/include/asm/arch-mpc85xx/gpio.h2
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index da7352a..41b6677 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -14,6 +14,8 @@
#ifndef __ASM_ARCH_MX85XX_GPIO_H
#define __ASM_ARCH_MX85XX_GPIO_H
+#ifndef CONFIG_MPC85XX_GPIO
#include <asm/mpc85xx_gpio.h>
+#endif
#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 07d2adf..c045a24 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -265,6 +265,7 @@ typedef struct ccsr_pcix {
#define PIWAR_WRITE_SNOOP 0x00005000
#define PIWAR_MEM_2G 0x0000001e
+#ifndef CONFIG_MPC85XX_GPIO
typedef struct ccsr_gpio {
u32 gpdir;
u32 gpodr;
@@ -273,6 +274,7 @@ typedef struct ccsr_gpio {
u32 gpimr;
u32 gpicr;
} ccsr_gpio_t;
+#endif
/* L2 Cache Registers */
typedef struct ccsr_l2cache {