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authorBoschung, Rainer <Rainer.Boschung@keymile.com>2014-06-03 09:05:13 +0200
committerYork Sun <yorksun@freescale.com>2014-08-01 14:18:07 -0700
commit60b295672d61fe79e6af3d9e4f3e8bd23bf3b4ad (patch)
tree3ec0fd58ef11a66a91fc9006999eab7333150904 /arch/powerpc
parent3345d18d5baad05807ecac36bc4125dbc74d288f (diff)
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powerpc: macros for e500mc timer regs added
For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/include/asm/processor.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 2445acd..1b98e0f 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -378,11 +378,16 @@
#else
#define SPRN_TCR 0x154 /* Book E Timer Control Register */
#endif /* CONFIG_BOOKE */
+#ifdef CONFIG_E500MC
+#define TCR_WP(x) (((64-x)&0x3)<<30)| \
+ (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
+#else
#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
#define WP_2_17 0 /* 2^17 clocks */
#define WP_2_21 1 /* 2^21 clocks */
#define WP_2_25 2 /* 2^25 clocks */
#define WP_2_29 3 /* 2^29 clocks */
+#endif /* CONFIG_E500 */
#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
#define WRC_NONE 0 /* No reset will occur */
#define WRC_CORE 1 /* Core reset will occur */