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authorTimur Tabi <timur@freescale.com>2011-10-31 13:30:43 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-11-08 08:31:02 -0600
commit452ad61c3feeffbf2b5ff74f0a6797af3ba4882c (patch)
tree62d4ea07003a0c2576467731a4e14e025a66c385 /arch/powerpc
parentc2efa0aa1e484448d553b37df9738095b113a71c (diff)
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powerpc/85xx: add some missing sync instructions in the CCSR relocation code
Calls to tlbwe and tlbsx should be preceded with an isync/msync pair. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 275accc..e519f35 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -352,6 +352,8 @@ purge_old_ccsr_tlb:
li r1, 0
mtspr MAS6, r1 /* Search the current address space and PID */
+ isync
+ msync
tlbsx 0, r8
mfspr r1, MAS1
andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */
@@ -359,6 +361,8 @@ purge_old_ccsr_tlb:
rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */
mtspr MAS1, r1
+ isync
+ msync
tlbwe
1: