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authorPrabhakar Kushwaha <prabhakar@freescale.com>2012-04-29 23:56:56 +0000
committerAndy Fleming <afleming@freescale.com>2012-07-06 17:30:30 -0500
commitd16a37b86459331faf5e31ef837f3dfb8d3411e3 (patch)
tree75f144255460f301c270d845420a4a1f5c58450e /arch/powerpc
parent689f00fc7e65d90222890c2ac4225137002db846 (diff)
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powerpc/85xx:Fix NAND code base to support debugger
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address. As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to any fetchable valid data Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 4267196..6aabc30 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -182,7 +182,7 @@ l2_disabled:
andi. r1,r3,L1CSR0_DCE@l
beq 2b
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception