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authorWolfgang Denk <wd@denx.de>2011-11-04 15:55:21 +0000
committerWolfgang Denk <wd@denx.de>2011-11-07 22:11:42 +0100
commit90357f14938806010841cad6c7782bf3b91b0c46 (patch)
tree3fd496318f16ba78e17d8fdadcaff6baa49e56a5 /arch/powerpc
parenta9a62af1f93986174be852ee68d2b524278563cf (diff)
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mpc8xx/fec.c: Fix GCC 4.6 build warnings
Fix: fec.c: In function 'fec_pin_init': fec.c:381:18: warning: variable 'fecp' set but not used [-Wunused-but-set-variable] fec.c: In function 'fec8xx_miiphy_write': fec.c:1013:8: warning: variable 'rdreg' set but not used [-Wunused-but-set-variable] Note: The code was slightly rearranged, but no functional changes attempted, i. e. no conversion to use I/O accessors. Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/cpu/mpc8xx/fec.c47
1 files changed, 25 insertions, 22 deletions
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index a2d2bd6..f2a2c3a 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -378,35 +378,39 @@ static void fec_pin_init(int fecidx)
{
bd_t *bd = gd->bd;
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec_t *fecp;
-
- /*
- * only two FECs please
- */
- if ((unsigned int)fecidx >= 2)
- hang();
-
- if (fecidx == 0)
- fecp = &immr->im_cpm.cp_fec1;
- else
- fecp = &immr->im_cpm.cp_fec2;
/*
* Set MII speed to 2.5 MHz or slightly below.
- * * According to the MPC860T (Rev. D) Fast ethernet controller user
- * * manual (6.2.14),
- * * the MII management interface clock must be less than or equal
- * * to 2.5 MHz.
- * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
- * * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
+ *
+ * According to the MPC860T (Rev. D) Fast ethernet controller user
+ * manual (6.2.14),
+ * the MII management interface clock must be less than or equal
+ * to 2.5 MHz.
+ * This MDC frequency is equal to system clock / (2 * MII_SPEED).
+ * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
*
* All MII configuration is done via FEC1 registers:
*/
immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
- /* our PHYs are the limit at 2.5 MHz */
- fecp->fec_mii_speed <<= 1;
+ {
+ volatile fec_t *fecp;
+
+ /*
+ * only two FECs please
+ */
+ if ((unsigned int)fecidx >= 2)
+ hang();
+
+ if (fecidx == 0)
+ fecp = &immr->im_cpm.cp_fec1;
+ else
+ fecp = &immr->im_cpm.cp_fec2;
+
+ /* our PHYs are the limit at 2.5 MHz */
+ fecp->fec_mii_speed <<= 1;
+ }
#endif
#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
@@ -1010,11 +1014,10 @@ int fec8xx_miiphy_read(const char *devname, unsigned char addr,
int fec8xx_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
- short rdreg; /* register working value */
#ifdef MII_DEBUG
printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
- rdreg = mii_send(mk_mii_write(addr, reg, value));
+ (void)mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf ("0x%04x\n", value);