Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

47 files changed, 3412 insertions, 464 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 33e93c8..78c412d 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,6 +66,9 @@ COBJS-$(CONFIG_PPC_P2041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_T4240)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_B4860)	+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
@@ -80,10 +83,14 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
 
 COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o
-COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
 # SoC specific SERDES support
 COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
@@ -110,6 +117,9 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
 
 COBJS	= $(COBJS-y)
 COBJS	+= cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
new file mode 100644
index 0000000..7d33731
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO(1, 27, 1, 0),
+	SET_QP_INFO(2, 28, 1, 0),
+	SET_QP_INFO(3, 29, 1, 1),
+	SET_QP_INFO(4, 30, 1, 1),
+	SET_QP_INFO(5, 31, 1, 2),
+	SET_QP_INFO(6, 32, 1, 2),
+	SET_QP_INFO(7, 33, 1, 3),
+	SET_QP_INFO(8, 34, 1, 3),
+	SET_QP_INFO(9, 35, 1, 0),
+	SET_QP_INFO(10, 36, 1, 0),
+	SET_QP_INFO(11, 37, 1, 1),
+	SET_QP_INFO(12, 38, 1, 1),
+	SET_QP_INFO(13, 39, 1, 2),
+	SET_QP_INFO(14, 40, 1, 2),
+	SET_QP_INFO(15, 41, 1, 3),
+	SET_QP_INFO(16, 42, 1, 3),
+	SET_QP_INFO(17, 43, 1, 0),
+	SET_QP_INFO(18, 44, 1, 0),
+	SET_QP_INFO(19, 45, 1, 1),
+	SET_QP_INFO(20, 46, 1, 1),
+	SET_QP_INFO(21, 47, 1, 2),
+	SET_QP_INFO(22, 48, 1, 2),
+	SET_QP_INFO(23, 49, 1, 3),
+	SET_QP_INFO(24, 50, 1, 3),
+	SET_QP_INFO(25, 51, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+	SET_SRIO_LIODN_1(1, 307),
+	SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(62),
+	SET_BMAN_LIODN(63),
+#endif
+
+	SET_SDHC_LIODN(1, 552),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+
+	SET_DMA_LIODN(1, 147),
+	SET_DMA_LIODN(2, 227),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+	/* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 88),
+	SET_FMAN_RX_1G_LIODN(1, 1, 89),
+	SET_FMAN_RX_1G_LIODN(1, 2, 90),
+	SET_FMAN_RX_1G_LIODN(1, 3, 91),
+	SET_FMAN_RX_1G_LIODN(1, 4, 92),
+	SET_FMAN_RX_1G_LIODN(1, 5, 93),
+	SET_FMAN_RX_10G_LIODN(1, 0, 94),
+	SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+	SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+	SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+	SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+	SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+	SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+	SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+	SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+	SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+	SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+	SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+	SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+	/* Set RMan block 0-3 liodn offset */
+	SET_RMAN_LIODN(0, 678),
+	SET_RMAN_LIODN(1, 679),
+	SET_RMAN_LIODN(2, 680),
+	SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+	[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
new file mode 100644
index 0000000..9990202
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+	u8 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x0E, {CPRI8, CPRI7,	CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x12, {CPRI8, CPRI7,	CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x30, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x32, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x33, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x34, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x3E, {CPRI8, CPRI7,	CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		AURORA, AURORA,	SRIO1, SRIO1}},
+	{0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		AURORA, AURORA,	SRIO1, SRIO1}},
+	{0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		AURORA, AURORA, SRIO1, SRIO1}},
+	{0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		AURORA, AURORA,
+		SRIO1, SRIO1}},
+	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2, AURORA, AURORA,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2, AURORA, AURORA,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{0x9E, {PCIE1, PCIE1,	PCIE1, PCIE1,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{0x9A, {PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+	serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index e8989bd..2be192d 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -76,11 +76,15 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
 	puts("Work-around for Erratum ESDHC111 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+	puts("Work-around for Erratum A004468 enabled\n");
+#endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
 	puts("Work-around for Erratum ESDHC135 enabled\n");
 #endif
-#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
-	puts("Work-around for Erratum ESDHC136 enabled\n");
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
+	if (SVR_MAJ(svr) < 3)
+		puts("Work-around for Erratum ESDHC13 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
 	puts("Work-around for Erratum ESDHC-A001 enabled\n");
@@ -127,6 +131,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 	puts("Work-around for Erratum A004510 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+	puts("Work-around for Erratum SRIO-A004034 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+	puts("Work-around for Erratum A004934 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 5ddb294..db232e6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -60,20 +60,32 @@ int checkcpu (void)
 	uint major, minor;
 	struct cpu_type *cpu;
 	char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if (defined(CONFIG_DDR_CLK_FREQ) || \
+	defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
-	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
-		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#else
+
+	/*
+	 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
+	 * mode. Previous platform use ddr ratio to do the same. This
+	 * information is only for display here.
+	 */
 #ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	u32 ddr_sync = 0;	/* only async mode is supported */
+#else
 	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
 		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#else	/* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
+	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 #else
 	u32 ddr_ratio = 0;
-#endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
+#endif /* CONFIG_FSL_CORENET */
+
 	unsigned int i, core, nr_cores = cpu_numcores();
 	u32 mask = cpu_mask();
 
@@ -127,6 +139,11 @@ int checkcpu (void)
 
 	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 
+	if (nr_cores > CONFIG_MAX_CPUS) {
+		panic("\nUnexpected number of cores: %d, max is %d\n",
+			nr_cores, CONFIG_MAX_CPUS);
+	}
+
 	get_sys_info(&sysinfo);
 
 	puts("Clock Configuration:");
@@ -181,6 +198,10 @@ int checkcpu (void)
 	}
 #endif
 
+#if defined(CONFIG_FSL_IFC)
+	printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+#endif
+
 #ifdef CONFIG_CPM2
 	printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 #endif
@@ -196,6 +217,10 @@ int checkcpu (void)
 	}
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	printf("       QMAN:  %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
+#endif
+
 #ifdef CONFIG_SYS_DPAA_PME
 	printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freqPME));
 #endif
@@ -270,10 +295,7 @@ reset_85xx_watchdog(void)
 	/*
 	 * Clear TSR(WIS) bit by writing 1
 	 */
-	unsigned long val;
-	val = mfspr(SPRN_TSR);
-	val |= TSR_WIS;
-	mtspr(SPRN_TSR, val);
+	mtspr(SPRN_TSR, TSR_WIS);
 }
 #endif	/* CONFIG_WATCHDOG */
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index afb5671..736293c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -295,6 +295,43 @@ static void __fsl_serdes__init(void)
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int enable_cluster_l2(void)
+{
+	int i = 0;
+	u32 cluster;
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct ccsr_cluster_l2 __iomem *l2cache;
+
+	cluster = in_be32(&gur->tp_cluster[i].lower);
+	if (cluster & TP_CLUSTER_EOC)
+		return 0;
+
+	/* The first cache has already been set up, so skip it */
+	i++;
+
+	/* Look through the remaining clusters, and set up their caches */
+	do {
+		l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+		cluster = in_be32(&gur->tp_cluster[i].lower);
+
+		/* set stash ID to (cluster) * 2 + 32 + 1 */
+		clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+
+		printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+		out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+		while ((in_be32(&l2cache->l2csr0) &
+			(L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+			;
+		out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+		i++;
+	} while (!(cluster & TP_CLUSTER_EOC));
+
+	return 0;
+}
+#endif
+
 /*
  * Initialize L2 as cache.
  *
@@ -306,7 +343,12 @@ int cpu_init_r(void)
 {
 	__maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_SYS_LBC_LCRR
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
+#endif
+#ifdef CONFIG_L2_CACHE
+	ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+	struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
 
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
@@ -356,7 +398,6 @@ int cpu_init_r(void)
 	puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)
-	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;
 	uint ver;
 	u32 l2siz_field;
@@ -467,6 +508,11 @@ int cpu_init_r(void)
 	}
 
 skip_l2:
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+	if (l2cache->l2csr0 & L2CSR0_L2E)
+		printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
+
+	enable_cluster_l2();
 #else
 	puts("disabled\n");
 #endif
@@ -478,7 +524,7 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 
 	char *s = getenv("bootmaster");
 	if (s) {
 		if (!strcmp(s, "SRIO1")) {
@@ -497,11 +543,13 @@ skip_l2:
 	setup_mp();
 #endif
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
 	{
-		void *p;
-		p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
-		setbits_be32(p, 1 << (31 - 14));
+		if (SVR_MAJ(svr) < 3) {
+			void *p;
+			p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+			setbits_be32(p, 1 << (31 - 14));
+		}
 	}
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index ca4ed62..f118dd5 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -18,12 +18,14 @@
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 			     unsigned int ctrl_num)
 {
-	unsigned int i;
+	unsigned int i, bus_width;
 	volatile ccsr_ddr_t *ddr;
 	u32 temp_sdram_cfg;
+	u32 total_gb_size_per_controller;
+	int timeout;
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	int timeout_save;
 	volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
-	u32 total_gb_size_per_controller;
 	unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
 	int csn = -1;
 #endif
@@ -52,8 +54,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		return;
 	}
 
-	out_be32(&ddr->eor, regs->ddr_eor);
-
+	if (regs->ddr_eor)
+		out_be32(&ddr->eor, regs->ddr_eor);
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 	debug("Workaround for ERRATUM_DDR111_DDR134\n");
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
@@ -121,6 +123,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 	out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 	out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+	if (regs->ddr_wrlvl_cntl_2)
+		out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+	if (regs->ddr_wrlvl_cntl_3)
+		out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+
 	out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 	out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 	out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
@@ -134,6 +141,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 			out_be32(&ddr->debug[i], regs->debug[i]);
 		}
 	}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+	out_be32(&ddr->debug[28], 0x00003000);
+#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 	out_be32(&ddr->debug[12], 0x00000015);
@@ -270,9 +280,48 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 	asm volatile("sync;isync");
 
+	total_gb_size_per_controller = 0;
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (!(regs->cs[i].config & 0x80000000))
+			continue;
+		total_gb_size_per_controller += 1 << (
+			((regs->cs[i].config >> 14) & 0x3) + 2 +
+			((regs->cs[i].config >> 8) & 0x7) + 12 +
+			((regs->cs[i].config >> 0) & 0x7) + 8 +
+			3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+			26);			/* minus 26 (count of 64M) */
+	}
+	if (fsl_ddr_get_intl3r() & 0x80000000)	/* 3-way interleaving */
+		total_gb_size_per_controller *= 3;
+	else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
+		total_gb_size_per_controller <<= 1;
+	/*
+	 * total memory / bus width = transactions needed
+	 * transactions needed / data rate = seconds
+	 * to add plenty of buffer, double the time
+	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+	 * Let's wait for 800ms
+	 */
+	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+			>> SDRAM_CFG_DBW_SHIFT);
+	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+		(get_ddr_freq(0) >> 20)) << 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	timeout_save = timeout;
+#endif
+	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
+	debug("total %d GB\n", total_gb_size_per_controller);
+	debug("Need to wait up to %d * 10ms\n", timeout);
+
 	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
-	while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
+	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+		(timeout >= 0)) {
 		udelay(10000);		/* throttle polling rate */
+		timeout--;
+	}
+
+	if (timeout <= 0)
+		printf("Waiting for D_INIT timeout. Memory may not work.\n");
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 	/* continue this workaround */
@@ -330,23 +379,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	while (in_be32(&ddr->debug[1]) & 0x400)
 		udelay(10000);          /* throttle polling rate */
 
-	/* 7. Wait for 400ms/GB */
-	total_gb_size_per_controller = 0;
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i == csn) {
-			total_gb_size_per_controller +=
-				((csn_bnds_backup & 0xFFFF) >> 6)
-				- (csn_bnds_backup >> 22) + 1;
-		} else {
-			total_gb_size_per_controller +=
-				((regs->cs[i].bnds & 0xFFFF) >> 6)
-				- (regs->cs[i].bnds >> 22) + 1;
-		}
-	}
-	if (in_be32(&ddr->sdram_cfg) & 0x80000)
-		total_gb_size_per_controller <<= 1;
-	debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
-	udelay(total_gb_size_per_controller * 400000);
+	/* 7. Wait for state machine 2nd run, roughly 400ms/GB */
+	debug("Wait for %d * 10ms\n", timeout_save);
+	udelay(timeout_save * 10000);
 
 	/* 8. Set sdram_cfg_2[dinit] if options requires */
 	setbits_be32(&ddr->sdram_cfg_2,
@@ -354,8 +389,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 
 	/* 9. Poll until dinit is cleared */
-	while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
-		udelay(10000);
+	timeout = timeout_save;
+	debug("Need to wait up to %d * 10ms\n", timeout);
+	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+		(timeout >= 0)) {
+		udelay(10000);		/* throttle polling rate */
+		timeout--;
+	}
+
+	if (timeout <= 0)
+		printf("Waiting for D_INIT timeout. Memory may not work.\n");
 
 	/* 10. Clear EEBACR[3] */
 	clrbits_be32(&ecm->eebacr, 10000000);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index a0a9b4c..ab09330 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -47,8 +47,8 @@ extern void ft_srio_setup(void *blob);
 void ft_fixup_cpu(void *blob, u64 memory_limit)
 {
 	int off;
-	ulong spin_tbl_addr = get_spin_phys_addr();
-	u32 bootpg = determine_mp_bootpg();
+	phys_addr_t spin_tbl_addr = get_spin_phys_addr();
+	u32 bootpg = determine_mp_bootpg(NULL);
 	u32 id = get_my_id();
 	const char *enable_method;
 
@@ -97,7 +97,16 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 	if ((u64)bootpg < memory_limit) {
 		off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
 		if (off < 0)
-			printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
+			printf("Failed to reserve memory for bootpg: %s\n",
+				fdt_strerror(off));
+	}
+	/* Reserve spin table page */
+	if (spin_tbl_addr < memory_limit) {
+		off = fdt_add_mem_rsv(blob,
+			(spin_tbl_addr & ~0xffful), 4096);
+		if (off < 0)
+			printf("Failed to reserve memory for spin table: %s\n",
+				fdt_strerror(off));
 	}
 }
 #endif
@@ -220,12 +229,19 @@ static inline void ft_fixup_l2cache(void *blob)
 
 	/* we dont bother w/L3 since no platform of this type has one */
 }
-#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+#elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
+	defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 static inline void ft_fixup_l2cache(void *blob)
 {
 	int off, l2_off, l3_off = -1;
 	u32 *ph;
+#ifdef	CONFIG_BACKSIDE_L2_CACHE
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
+#else
+	struct ccsr_cluster_l2 *l2cache =
+		(struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+	u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
+#endif
 	u32 size, line_size, num_ways, num_sets;
 	int has_l2 = 1;
 
@@ -257,7 +273,12 @@ static inline void ft_fixup_l2cache(void *blob)
 		if (has_l2) {
 #ifdef CONFIG_SYS_CACHE_STASHING
 			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+			/* Only initialize every eighth thread */
+			if (reg && !((*reg) % 8))
+#else
 			if (reg)
+#endif
 				fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 					 (*reg * 2) + 32 + 1);
 #endif
@@ -390,6 +411,11 @@ static void ft_fixup_dpaa_clks(void *blob)
 #endif
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	do_fixup_by_compat_u32(blob, "fsl,qman",
+			"clock-frequency", sysinfo.freqQMAN, 1);
+#endif
+
 #ifdef CONFIG_SYS_DPAA_PME
 	do_fixup_by_compat_u32(blob, "fsl,pme",
 		"clock-frequency", sysinfo.freqPME, 1);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
new file mode 100644
index 0000000..01dcdf6
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/fsl_law.h>
+#include <asm/errno.h>
+#include "fsl_corenet2_serdes.h"
+
+static u64 serdes1_prtcl_map;
+static u64 serdes2_prtcl_map;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+static u64 serdes3_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+static u64 serdes4_prtcl_map;
+#endif
+
+#ifdef DEBUG
+static const char *serdes_prtcl_str[] = {
+	[NONE] = "NA",
+	[PCIE1] = "PCIE1",
+	[PCIE2] = "PCIE2",
+	[PCIE3] = "PCIE3",
+	[PCIE4] = "PCIE4",
+	[SATA1] = "SATA1",
+	[SATA2] = "SATA2",
+	[SRIO1] = "SRIO1",
+	[SRIO2] = "SRIO2",
+	[SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
+	[SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
+	[SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
+	[SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
+	[SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
+	[SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
+	[SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
+	[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
+	[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
+	[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+	[XAUI_FM1] = "XAUI_FM1",
+	[XAUI_FM2] = "XAUI_FM2",
+	[AURORA] = "DEBUG",
+	[CPRI1] = "CPRI1",
+	[CPRI2] = "CPRI2",
+	[CPRI3] = "CPRI3",
+	[CPRI4] = "CPRI4",
+	[CPRI5] = "CPRI5",
+	[CPRI6] = "CPRI6",
+	[CPRI7] = "CPRI7",
+	[CPRI8] = "CPRI8",
+	[XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
+	[XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
+	[XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
+	[XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
+	[HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
+	[HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
+	[HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
+	[HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
+	[QSGMII_FM1_A] = "QSGMII_FM1_A",
+	[QSGMII_FM1_B] = "QSGMII_FM1_B",
+	[QSGMII_FM2_A] = "QSGMII_FM2_A",
+	[QSGMII_FM2_B] = "QSGMII_FM2_B",
+	[XFI_FM1_MAC9] = "XFI_FM1_MAC9",
+	[XFI_FM1_MAC10] = "XFI_FM1_MAC10",
+	[XFI_FM2_MAC9] = "XFI_FM2_MAC9",
+	[XFI_FM2_MAC10] = "XFI_FM2_MAC10",
+	[INTERLAKEN] = "INTERLAKEN",
+};
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+	u64 ret = 0;
+
+	ret |= (1ULL << device) & serdes1_prtcl_map;
+	ret |= (1ULL << device) & serdes2_prtcl_map;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+	ret |= (1ULL << device) & serdes3_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+	ret |= (1ULL << device) & serdes4_prtcl_map;
+#endif
+
+	return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+	const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 cfg = in_be32(&gur->rcwsr[4]);
+	int i;
+
+	switch (sd) {
+	case FSL_SRDS_1:
+		cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+		cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+		break;
+	case FSL_SRDS_2:
+		cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+		cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+		break;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+	case FSL_SRDS_3:
+		cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
+		cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
+		break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+	case FSL_SRDS_4:
+		cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
+		cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
+		break;
+#endif
+	default:
+		printf("invalid SerDes%d\n", sd);
+		break;
+	}
+	/* Is serdes enabled at all? */
+	if (unlikely(cfg == 0))
+		return -ENODEV;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_get_prtcl(sd, cfg, i) == device)
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u64 serdes_prtcl_map = 0;
+	u32 cfg;
+	int lane;
+
+	cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
+	/* Is serdes enabled at all? */
+	if (!cfg) {
+		printf("SERDES%d is not enabled\n", sd + 1);
+		return 0;
+	}
+
+	cfg >>= sd_prctl_shift;
+	printf("Using SERDES%d Protocol: 0x%x\n", sd + 1, cfg);
+	if (!is_serdes_prtcl_valid(sd, cfg))
+		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+		serdes_prtcl_map |= (1ULL << lane_prtcl);
+	}
+
+	return serdes_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+
+	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+		CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+		FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
+		FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+		FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
+		FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+#ifdef CONFIG_SYS_FSL_SRDS_3
+	serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
+		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+		FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
+		FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+	serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
+		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+		FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
+		FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
+#endif
+
+}
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
new file mode 100644
index 0000000..2258f41
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_CORENET2_SERDES_H
+#define __FSL_CORENET2_SERDES_H
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_lane_enabled(int lane);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+#endif /* __FSL_CORENET2_SERDES_H */
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2a68060..e6b1b1b 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -92,10 +92,17 @@ static const struct {
 	{ 17, 163, FSL_SRDS_BANK_2 },
 	{ 18, 164, FSL_SRDS_BANK_2 },
 	{ 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
 	{ 20, 170, FSL_SRDS_BANK_3 },
 	{ 21, 171, FSL_SRDS_BANK_3 },
 	{ 22, 172, FSL_SRDS_BANK_3 },
 	{ 23, 173, FSL_SRDS_BANK_3 },
+#else
+	{ 20, 166, FSL_SRDS_BANK_3 },
+	{ 21, 167, FSL_SRDS_BANK_3 },
+	{ 22, 168, FSL_SRDS_BANK_3 },
+	{ 23, 169, FSL_SRDS_BANK_3 },
+#endif
 };
 
 int serdes_get_lane_idx(int lane)
@@ -493,6 +500,9 @@ void fsl_serdes_init(void)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int cfg;
 	serdes_corenet_t *srds_regs;
+#ifdef CONFIG_PPC_P5040
+	serdes_corenet_t *srds2_regs;
+#endif
 	int lane, bank, idx;
 	int have_bank[SRDS_MAX_BANK] = {};
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -574,6 +584,34 @@ void fsl_serdes_init(void)
 		}
 	}
 
+#ifdef CONFIG_PPC_P5040
+	/*
+	 * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
+	 * protocols, these lanes are routed to SATA.  We use serdes_prtcl_map
+	 * to decide whether a protocol is supported on a given lane, so SATA
+	 * will be identified as not supported, and therefore not initialized.
+	 * So for protocols which use SATA on bank4, we add SATA support in
+	 * serdes_prtcl_map.
+	 */
+	switch (cfg) {
+	case 0x0:
+	case 0x1:
+	case 0x2:
+	case 0x3:
+	case 0x4:
+	case 0x5:
+	case 0x6:
+	case 0x7:
+		serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
+		break;
+	default:
+		srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+
+		/* We don't need bank 4, so power it down */
+		setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
+	}
+#endif
+
 	soc_serdes_init();
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -617,6 +655,38 @@ void fsl_serdes_init(void)
 		}
 	}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004699
+	/*
+	 * To avoid the situation that resulted in the P4080 erratum
+	 * SERDES-8, a given SerDes bank will use the PLLs from the previous
+	 * bank if one of the PLL frequencies is a multiple of the other.  For
+	 * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
+	 * then bank 3 will use bank 2's PLL.  P5040 Erratum A-004699 says
+	 * that, in this situation, lane synchronization is not initiated.  So
+	 * when we detect a bank with a "borrowed" PLL, we have to manually
+	 * initiate lane synchronization.
+	 */
+	for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
+		/* Determine the first lane for this bank */
+		unsigned int lane;
+
+		for (lane = 0; lane < SRDS_MAX_LANES; lane++)
+			if (lanes[lane].bank == bank)
+				break;
+		idx = lanes[lane].idx;
+
+		/*
+		 * Check if the PLL for the bank is borrowed.  The UOTHL
+		 * bit of the first lane will tell us that.
+		 */
+		if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
+			/* Manually start lane synchronization */
+			setbits_be32(&srds_regs->bank[bank].pllcr0,
+				     SRDS_PLLCR0_PVCOCNT_EN);
+		}
+	}
+#endif
+
 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 		enum srds_prtcl lane_prtcl;
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
index f261351..3c551e9 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
@@ -22,9 +22,6 @@
 #ifndef __FSL_CORENET_SERDES_H
 #define __FSL_CORENET_SERDES_H
 
-#define SRDS_MAX_LANES		18
-#define SRDS_MAX_BANK		3
-
 enum srds_bank {
 	FSL_SRDS_BANK_1  = 0,
 	FSL_SRDS_BANK_2  = 1,
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 11881c9..2e53367 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -40,6 +40,7 @@ int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset)
 	return liodn_bases[dpaa_dev].num_ids;
 }
 
+#ifdef CONFIG_SYS_SRIO
 static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size)
 {
 	int i;
@@ -54,6 +55,7 @@ static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size)
 		}
 	}
 }
+#endif
 
 static void set_liodn(struct liodn_id_table *tbl, int size)
 {
@@ -181,8 +183,10 @@ void set_liodns(void)
 	/* setup general liodn offsets */
 	set_liodn(liodn_tbl, liodn_tbl_sz);
 
+#ifdef CONFIG_SYS_SRIO
 	/* setup SRIO port liodns */
 	set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz);
+#endif
 
 	/* setup SEC block liodn bases & offsets if we have one */
 	if (IS_E_PROCESSOR(get_svr())) {
@@ -219,6 +223,7 @@ void set_liodns(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_SRIO
 static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
 {
 	int i, srio_off;
@@ -247,6 +252,57 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
 		}
 	}
 }
+#endif
+
+#define CONFIG_SYS_MAX_PCI_EPS		8
+#define CONFIG_SYS_PCI_EP_LIODN_START	256
+
+static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
+{
+	int off, pci_idx = 0, pci_cnt = 0, i, rc;
+	const uint32_t *base_liodn;
+	uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 };
+
+	/*
+	 * Count the number of pci nodes.
+	 * It's needed later when the interleaved liodn offsets are generated.
+	 */
+	off = fdt_node_offset_by_compatible(fdt, -1, compat);
+	while (off != -FDT_ERR_NOTFOUND) {
+		pci_cnt++;
+		off = fdt_node_offset_by_compatible(fdt, off, compat);
+	}
+
+	for (off = fdt_node_offset_by_compatible(fdt, -1, compat);
+	     off != -FDT_ERR_NOTFOUND;
+	     off = fdt_node_offset_by_compatible(fdt, off, compat)) {
+		base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc);
+		if (!base_liodn) {
+			char path[64];
+
+			if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+				strcpy(path, "(unknown)");
+			printf("WARNING Could not get liodn of node %s: %s\n",
+			       path, fdt_strerror(rc));
+			continue;
+		}
+		for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
+			liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
+					i * pci_cnt + pci_idx - *base_liodn;
+		rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
+				 liodn_offs, sizeof(liodn_offs));
+		if (rc) {
+			char path[64];
+
+			if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+				strcpy(path, "(unknown)");
+			printf("WARNING Unable to set fsl,liodn-offset-list for "
+			       "node %s: %s\n", path, fdt_strerror(rc));
+			continue;
+		}
+		pci_idx++;
+	}
+}
 
 static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
 {
@@ -277,7 +333,9 @@ static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
 
 void fdt_fixup_liodn(void *blob)
 {
+#ifdef CONFIG_SYS_SRIO
 	fdt_fixup_srio_liodn(blob, srio_liodn_tbl);
+#endif
 
 	fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz);
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -295,4 +353,6 @@ void fdt_fixup_liodn(void *blob)
 #ifdef CONFIG_SYS_DPAA_RMAN
 	fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
 #endif
+
+	fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
 }
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index ffc2a9a..e1197ac 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -27,9 +27,13 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
+u32 fsl_ddr_get_intl3r(void);
+
+extern u32 __spin_table[];
 
 u32 get_my_id()
 {
@@ -76,17 +80,16 @@ int cpu_status(int nr)
 		return 0;
 
 	if (nr == id) {
-		table = (u32 *)get_spin_virt_addr();
+		table = (u32 *)&__spin_table;
 		printf("table base @ 0x%p\n", table);
 	} else {
-		table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
+		table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
 		printf("Running on cpu %d\n", id);
 		printf("\n");
 		printf("table @ 0x%p\n", table);
 		printf("   addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
-		printf("   pir  - 0x%08x\n", table[BOOT_ENTRY_PIR]);
 		printf("   r3   - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
-		printf("   r6   - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
+		printf("   pir  - 0x%08x\n", table[BOOT_ENTRY_PIR]);
 	}
 
 	return 0;
@@ -149,12 +152,11 @@ static u8 boot_entry_map[4] = {
 	0,
 	BOOT_ENTRY_PIR,
 	BOOT_ENTRY_R3_LOWER,
-	BOOT_ENTRY_R6_LOWER,
 };
 
 int cpu_release(int nr, int argc, char * const argv[])
 {
-	u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
+	u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
 	u64 boot_addr;
 
 	if (hold_cores_in_reset(1))
@@ -172,8 +174,8 @@ int cpu_release(int nr, int argc, char * const argv[])
 
 	boot_addr = simple_strtoull(argv[0], NULL, 16);
 
-	/* handle pir, r3, r6 */
-	for (i = 1; i < 4; i++) {
+	/* handle pir, r3 */
+	for (i = 1; i < 3; i++) {
 		if (argv[i][0] != '-') {
 			u8 entry = boot_entry_map[i];
 			val = simple_strtoul(argv[i], NULL, 16);
@@ -191,38 +193,80 @@ int cpu_release(int nr, int argc, char * const argv[])
 	return 0;
 }
 
-u32 determine_mp_bootpg(void)
+u32 determine_mp_bootpg(unsigned int *pagesize)
 {
-	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
-	if ((u64)gd->ram_size > 0xfffff000)
-		return (0xfffff000);
+	u32 bootpg;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+	u32 svr = get_svr();
+	u32 granule_size, check;
+	struct law_entry e;
+#endif
 
-	return (gd->ram_size - 4096);
-}
 
-ulong get_spin_phys_addr(void)
-{
-	extern ulong __secondary_start_page;
-	extern ulong __spin_table;
+	/* use last 4K of mapped memory */
+	bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
+		CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
+		CONFIG_SYS_SDRAM_BASE - 4096;
+	if (pagesize)
+		*pagesize = 4096;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+/*
+ * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
+ * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
+ * the way boot page chosen in u-boot avoids hitting this erratum. So only
+ * thw workaround for 3-way interleaving is needed.
+ *
+ * To make sure boot page translation works with 3-Way DDR interleaving
+ * enforce a check for the following constrains
+ * 8K granule size requires BRSIZE=8K and
+ *    bootpg >> log2(BRSIZE) %3 == 1
+ * 4K and 1K granule size requires BRSIZE=4K and
+ *    bootpg >> log2(BRSIZE) %3 == 0
+ */
+	if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
+		e = find_law(bootpg);
+		switch (e.trgt_id) {
+		case LAW_TRGT_IF_DDR_INTLV_123:
+			granule_size = fsl_ddr_get_intl3r() & 0x1f;
+			if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
+				if (pagesize)
+					*pagesize = 8192;
+				bootpg &= 0xffffe000;	/* align to 8KB */
+				check = bootpg >> 13;
+				while ((check % 3) != 1)
+					check--;
+				bootpg = check << 13;
+				debug("Boot page (8K) at 0x%08x\n", bootpg);
+				break;
+			} else {
+				bootpg &= 0xfffff000;	/* align to 4KB */
+				check = bootpg >> 12;
+				while ((check % 3) != 0)
+					check--;
+				bootpg = check << 12;
+				debug("Boot page (4K) at 0x%08x\n", bootpg);
+			}
+				break;
+		default:
+			break;
+		}
+	}
+#endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
 
-	return (determine_mp_bootpg() +
-		(ulong)&__spin_table - (ulong)&__secondary_start_page);
+	return bootpg;
 }
 
-ulong get_spin_virt_addr(void)
+phys_addr_t get_spin_phys_addr(void)
 {
-	extern ulong __secondary_start_page;
-	extern ulong __spin_table;
-
-	return (CONFIG_BPTR_VIRT_ADDR +
-		(ulong)&__spin_table - (ulong)&__secondary_start_page);
+	return virt_to_phys(&__spin_table);
 }
 
 #ifdef CONFIG_FSL_CORENET
-static void plat_mp_up(unsigned long bootpg)
+static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 {
-	u32 cpu_up_mask, whoami;
-	u32 *table = (u32 *)get_spin_virt_addr();
+	u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
+	u32 *table = (u32 *)&__spin_table;
 	volatile ccsr_gur_t *gur;
 	volatile ccsr_local_t *ccm;
 	volatile ccsr_rcpm_t *rcpm;
@@ -241,7 +285,11 @@ static void plat_mp_up(unsigned long bootpg)
 	out_be32(&ccm->bstrl, bootpg);
 
 	e = find_law(bootpg);
-	out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
+	/* pagesize is only 4K or 8K */
+	if (pagesize == 8192)
+		brsize = LAW_SIZE_8K;
+	out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
+	debug("BRSIZE is 0x%x\n", brsize);
 
 	/* readback to sync write */
 	in_be32(&ccm->bstrar);
@@ -294,10 +342,10 @@ static void plat_mp_up(unsigned long bootpg)
 #endif
 }
 #else
-static void plat_mp_up(unsigned long bootpg)
+static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 {
 	u32 up, cpu_up_mask, whoami;
-	u32 *table = (u32 *)get_spin_virt_addr();
+	u32 *table = (u32 *)&__spin_table;
 	volatile u32 bpcr;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -374,27 +422,52 @@ static void plat_mp_up(unsigned long bootpg)
 
 void cpu_mp_lmb_reserve(struct lmb *lmb)
 {
-	u32 bootpg = determine_mp_bootpg();
+	u32 bootpg = determine_mp_bootpg(NULL);
 
 	lmb_reserve(lmb, bootpg, 4096);
 }
 
 void setup_mp(void)
 {
-	extern ulong __secondary_start_page;
-	extern ulong __bootpg_addr;
-	ulong fixup = (ulong)&__secondary_start_page;
-	u32 bootpg = determine_mp_bootpg();
+	extern u32 __secondary_start_page;
+	extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
+
+	int i;
+	ulong fixup = (u32)&__secondary_start_page;
+	u32 bootpg, bootpg_map, pagesize;
+
+	bootpg = determine_mp_bootpg(&pagesize);
+
+	/*
+	 * pagesize is only 4K or 8K
+	 * we only use the last 4K of boot page
+	 * bootpg_map saves the address for the boot page
+	 * 8K is used for the workaround of 3-way DDR interleaving
+	 */
+
+	bootpg_map = bootpg;
+
+	if (pagesize == 8192)
+		bootpg += 4096;	/* use 2nd half */
 
 	/* Some OSes expect secondary cores to be held in reset */
 	if (hold_cores_in_reset(0))
 		return;
 
-	/* Store the bootpg's SDRAM address for use by secondary CPU cores */
-	__bootpg_addr = bootpg;
+	/*
+	 * Store the bootpg's cache-able half address for use by secondary
+	 * CPU cores to continue to boot
+	 */
+	__bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
+
+	/* Store spin table's physical address for use by secondary cores */
+	__spin_table_addr = (u32)get_spin_phys_addr();
+
+	/* flush bootpg it before copying invalidate any staled cacheline */
+	flush_cache(bootpg, 4096);
 
 	/* look for the tlb covering the reset page, there better be one */
-	int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+	i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
 
 	/* we found a match */
 	if (i != -1) {
@@ -407,7 +480,7 @@ void setup_mp(void)
 
 		memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
 
-		plat_mp_up(bootpg);
+		plat_mp_up(bootpg_map, pagesize);
 	} else {
 		puts("WARNING: No reset page TLB. "
 			"Skipping secondary core setup\n");
diff --git a/arch/powerpc/cpu/mpc85xx/mp.h b/arch/powerpc/cpu/mpc85xx/mp.h
index 87bac37..ad9950b 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.h
+++ b/arch/powerpc/cpu/mpc85xx/mp.h
@@ -3,8 +3,7 @@
 
 #include <asm/mp.h>
 
-ulong get_spin_phys_addr(void);
-ulong get_spin_virt_addr(void);
+phys_addr_t get_spin_phys_addr(void);
 u32 get_my_id(void);
 int hold_cores_in_reset(int verbose);
 
@@ -16,7 +15,7 @@ int hold_cores_in_reset(int verbose);
 #define BOOT_ENTRY_PIR		5
 #define BOOT_ENTRY_R6_UPPER	6
 #define BOOT_ENTRY_R6_LOWER	7
-#define NUM_BOOT_ENTRY		8
+#define NUM_BOOT_ENTRY		16	/* pad to 64 bytes */
 #define SIZE_BOOT_ENTRY		(NUM_BOOT_ENTRY * sizeof(u32))
 
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
new file mode 100644
index 0000000..878ee3e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO(1, 2, 1, 0),
+	SET_QP_INFO(3, 4, 2, 1),
+	SET_QP_INFO(5, 6, 3, 2),
+	SET_QP_INFO(7, 8, 4, 3),
+	SET_QP_INFO(9, 10, 5, 0),
+	SET_QP_INFO(11, 12, 6, 1),
+	SET_QP_INFO(13, 14, 7, 2),
+	SET_QP_INFO(15, 16, 8, 3),
+	SET_QP_INFO(17, 18, 9, 0),	/* for now, set sdest to 0 */
+	SET_QP_INFO(19, 20, 10, 0),	/* for now, set sdest to 0 */
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(31),
+	SET_BMAN_LIODN(32),
+#endif
+
+	SET_SDHC_LIODN(1, 64),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 93),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 94),
+
+	SET_SATA_LIODN(1, 95),
+	SET_SATA_LIODN(2, 96),
+
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 195),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197),
+
+	SET_DMA_LIODN(1, 193),
+	SET_DMA_LIODN(2, 194),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 6),
+	SET_FMAN_RX_1G_LIODN(1, 1, 7),
+	SET_FMAN_RX_1G_LIODN(1, 2, 8),
+	SET_FMAN_RX_1G_LIODN(1, 3, 9),
+	SET_FMAN_RX_1G_LIODN(1, 4, 10),
+	SET_FMAN_RX_10G_LIODN(1, 0, 11),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(2, 0, 12),
+	SET_FMAN_RX_1G_LIODN(2, 1, 13),
+	SET_FMAN_RX_1G_LIODN(2, 2, 14),
+	SET_FMAN_RX_1G_LIODN(2, 3, 15),
+	SET_FMAN_RX_1G_LIODN(2, 4, 16),
+	SET_FMAN_RX_10G_LIODN(2, 0, 17),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 89),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 90),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 91),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 92),
+	SET_SEC_DECO_LIODN_ENTRY(0, 139, 140),
+	SET_SEC_DECO_LIODN_ENTRY(1, 141, 142),
+	SET_SEC_DECO_LIODN_ENTRY(2, 143, 144),
+	SET_SEC_DECO_LIODN_ENTRY(3, 145, 146),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct liodn_id_table raide_liodn_tbl[] = {
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
+};
+int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 101),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160),
+#endif
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	[FSL_HW_PORTAL_RAID_ENGINE]  = SET_LIODN_BASE_1(49),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
new file mode 100644
index 0000000..890b88e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+/*
+ * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
+ * U-boot only supports one SerDes controller.  Therefore, we ignore bank 4 in
+ * this table.  This works because most of the SerDes code is for errata
+ * work-arounds, and there are no P5040 errata that effect bank 4.
+ */
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+	[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
+	[0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
+		XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
+		SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		/* SATA1, SATA2 */ },
+	[0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
+		SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		/* SATA1, SATA2 */ },
+	[0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
+		XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
+		/* NONE, NONE */ },
+	[0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+		NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
+	[0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+		AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
+	[0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+		AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+		NONE, SATA1, SATA2, /* NONE, NONE */ },
+	[0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
+		/* NONE, NONE */ },
+	[0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+		AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+		NONE, SATA1, SATA2, /* NONE, NONE */ },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+	if (!serdes_lane_enabled(lane))
+		return NONE;
+
+	return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl)
+{
+	int i;
+
+	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_cfg_tbl[prtcl][i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 6199633..b59ef69 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -182,14 +182,18 @@ void fdt_fixup_qportals(void *blob)
 {
 	int off, err;
 	unsigned int maj, min;
+	unsigned int ip_cfg;
 	u32 rev_1 = in_be32(&qman->ip_rev_1);
+	u32 rev_2 = in_be32(&qman->ip_rev_2);
 	char compat[64];
 	int compat_len;
 
 	maj = (rev_1 >> 8) & 0xff;
 	min = rev_1 & 0xff;
+	ip_cfg = rev_2 & 0xff;
 
-	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u", maj, min) + 1;
+	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
+					maj, min, ip_cfg) + 1;
 	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
 
 	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
@@ -267,14 +271,19 @@ void fdt_fixup_bportals(void *blob)
 {
 	int off, err;
 	unsigned int maj, min;
+	unsigned int ip_cfg;
 	u32 rev_1 = in_be32(&bman->ip_rev_1);
+	u32 rev_2 = in_be32(&bman->ip_rev_2);
 	char compat[64];
 	int compat_len;
 
 	maj = (rev_1 >> 8) & 0xff;
 	min = rev_1 & 0xff;
 
-	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u", maj, min) + 1;
+	ip_cfg = rev_2 & 0xff;
+
+	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
+				 maj, min, ip_cfg) + 1;
 	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
 
 	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 22e73e0..4ba44a9 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -150,29 +150,33 @@ __secondary_start_page:
 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
 
 	/* get our PIR to figure out our table entry */
-	lis	r3,toreset(__spin_table)@h
-	ori	r3,r3,toreset(__spin_table)@l
+	lis	r3,toreset(__spin_table_addr)@h
+	ori	r3,r3,toreset(__spin_table_addr)@l
+	lwz	r3,0(r3)
 
-	/* r10 has the base address for the entry */
+	/*
+	 * r10 has the base address for the entry.
+	 * we cannot access it yet before setting up a new TLB
+	 */
 	mfspr	r0,SPRN_PIR
 #if	defined(CONFIG_E6500)
 /*
  * PIR definition for E6500
  * 0-17 Reserved (logic 0s)
- * 8-19 CHIP_ID,    2’b00      - SoC 1
+ * 8-19 CHIP_ID,    2'b00      - SoC 1
  *                  all others - reserved
- * 20-24 CLUSTER_ID 5’b00000   - CCM 1
+ * 20-24 CLUSTER_ID 5'b00000   - CCM 1
  *                  all others - reserved
- * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1
- *                       2’b01 - cluster 2
- *                       2’b10 - cluster 3
- *                       2’b11 - cluster 4
- * 27-28 CORE_ID         2’b00 - core 0
- *                       2’b01 - core 1
- *                       2’b10 - core 2
- *                       2’b11 - core 3
- * 29-31 THREAD_ID       3’b000 - thread 0
- *                       3’b001 - thread 1
+ * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
+ *                       2'b01 - cluster 2
+ *                       2'b10 - cluster 3
+ *                       2'b11 - cluster 4
+ * 27-28 CORE_ID         2'b00 - core 0
+ *                       2'b01 - core 1
+ *                       2'b10 - core 2
+ *                       2'b11 - core 3
+ * 29-31 THREAD_ID       3'b000 - thread 0
+ *                       3'b001 - thread 1
  */
 	rlwinm  r4,r0,29,25,31
 #elif	defined(CONFIG_E500MC)
@@ -180,16 +184,9 @@ __secondary_start_page:
 #else
 	mr	r4,r0
 #endif
-	slwi	r8,r4,5
+	slwi	r8,r4,6	/* spin table is padded to 64 byte */
 	add	r10,r3,r8
 
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
-	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
-	slwi	r8,r4,1
-	addi	r8,r8,32
-	mtspr	L1CSR2,r8
-#endif
-
 #ifdef CONFIG_E6500
 	mfspr	r0,SPRN_PIR
 	/*
@@ -209,6 +206,13 @@ __secondary_start_page:
 
 	mtspr	SPRN_PIR,r4	/* write to PIR register */
 
+#ifdef CONFIG_SYS_CACHE_STASHING
+	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+	slwi	r8,r4,1
+	addi	r8,r8,32
+	mtspr	L1CSR2,r8
+#endif
+
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 	/*
@@ -277,73 +281,111 @@ __secondary_start_page:
 	beq	2b
 #endif
 3:
-
-#define EPAPR_MAGIC		(0x45504150)
-#define ENTRY_ADDR_UPPER	0
-#define ENTRY_ADDR_LOWER	4
-#define ENTRY_R3_UPPER		8
-#define ENTRY_R3_LOWER		12
-#define ENTRY_RESV		16
-#define ENTRY_PIR		20
-#define ENTRY_R6_UPPER		24
-#define ENTRY_R6_LOWER		28
-#define ENTRY_SIZE		32
-
-	/* setup the entry */
-	li	r3,0
-	li	r8,1
-	stw	r4,ENTRY_PIR(r10)
-	stw	r3,ENTRY_ADDR_UPPER(r10)
-	stw	r8,ENTRY_ADDR_LOWER(r10)
-	stw	r3,ENTRY_R3_UPPER(r10)
-	stw	r4,ENTRY_R3_LOWER(r10)
-	stw	r3,ENTRY_R6_UPPER(r10)
-	stw	r3,ENTRY_R6_LOWER(r10)
-
-	/* load r13 with the address of the 'bootpg' in SDRAM */
-	lis	r13,toreset(__bootpg_addr)@h
-	ori	r13,r13,toreset(__bootpg_addr)@l
+	/* setup mapping for the spin table, WIMGE=0b00100 */
+	lis	r13,toreset(__spin_table_addr)@h
+	ori	r13,r13,toreset(__spin_table_addr)@l
 	lwz	r13,0(r13)
+	/* mask by 4K */
+	rlwinm	r13,r13,0,0,19
 
-	/* setup mapping for AS = 1, and jump there */
 	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
 	mtspr	SPRN_MAS0,r11
 	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
 	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 	mtspr	SPRN_MAS1,r11
-	oris	r11,r13,(MAS2_I|MAS2_G)@h
-	ori	r11,r13,(MAS2_I|MAS2_G)@l
+	oris	r11,r13,(MAS2_M|MAS2_G)@h
+	ori	r11,r13,(MAS2_M|MAS2_G)@l
 	mtspr	SPRN_MAS2,r11
 	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
 	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
 	mtspr	SPRN_MAS3,r11
+	li	r11,0
+	mtspr	SPRN_MAS7,r11
 	tlbwe
 
-	bl	1f
-1:	mflr	r11
 	/*
-	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
-	 * this mask to fixup the cpu spin table and the address that we want
-	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
-	 * bootpg is at 0x7ffff000 in SDRAM.
+	 * __bootpg_addr has the address of __second_half_boot_page
+	 * jump there in AS=1 space with cache enabled
 	 */
-	ori	r13,r13,0xfff
-	and	r11, r11, r13
-	and	r10, r10, r13
-
-	addi	r11,r11,(2f-1b)
+	lis	r13,toreset(__bootpg_addr)@h
+	ori	r13,r13,toreset(__bootpg_addr)@l
+	lwz	r11,0(r13)
+	mtspr	SPRN_SRR0,r11
 	mfmsr	r13
 	ori	r12,r13,MSR_IS|MSR_DS@l
-
-	mtspr	SPRN_SRR0,r11
 	mtspr	SPRN_SRR1,r12
 	rfi
 
+	/*
+	 * Allocate some space for the SDRAM address of the bootpg.
+	 * This variable has to be in the boot page so that it can
+	 * be accessed by secondary cores when they come out of reset.
+	 */
+	.align L1_CACHE_SHIFT
+	.globl __bootpg_addr
+__bootpg_addr:
+	.long	0
+
+	.global __spin_table_addr
+__spin_table_addr:
+	.long	0
+
+	/*
+	 * This variable is set by cpu_init_r() after parsing hwconfig
+	 * to enable workaround for erratum NMG_CPU_A011.
+	 */
+	.align L1_CACHE_SHIFT
+	.global enable_cpu_a011_workaround
+enable_cpu_a011_workaround:
+	.long	1
+
+	/* Fill in the empty space.  The actual reset vector is
+	 * the last word of the page */
+__secondary_start_code_end:
+	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
+__secondary_reset_vector:
+	b	__secondary_start_page
+
+
+/* this is a separated page for the spin table and cacheable boot code */
+	.align L1_CACHE_SHIFT
+	.global __second_half_boot_page
+__second_half_boot_page:
+#define EPAPR_MAGIC		0x45504150
+#define ENTRY_ADDR_UPPER	0
+#define ENTRY_ADDR_LOWER	4
+#define ENTRY_R3_UPPER		8
+#define ENTRY_R3_LOWER		12
+#define ENTRY_RESV		16
+#define ENTRY_PIR		20
+#define ENTRY_SIZE		64
+	/*
+	 * setup the entry
+	 * r10 has the base address of the spin table.
+	 * spin table is defined as
+	 * struct {
+	 *	uint64_t entry_addr;
+	 *	uint64_t r3;
+	 *	uint32_t rsvd1;
+	 *	uint32_t pir;
+	 * };
+	 * we pad this struct to 64 bytes so each entry is in its own cacheline
+	 */
+	li	r3,0
+	li	r8,1
+	mfspr	r4,SPRN_PIR
+	stw	r3,ENTRY_ADDR_UPPER(r10)
+	stw	r3,ENTRY_R3_UPPER(r10)
+	stw	r4,ENTRY_R3_LOWER(r10)
+	stw	r3,ENTRY_RESV(r10)
+	stw	r4,ENTRY_PIR(r10)
+	msync
+	stw	r8,ENTRY_ADDR_LOWER(r10)
+
 	/* spin waiting for addr */
-2:
-	lwz	r4,ENTRY_ADDR_LOWER(r10)
+3:	lwz	r4,ENTRY_ADDR_LOWER(r10)
 	andi.	r11,r4,1
-	bne	2b
+	bne	3b
 	isync
 
 	/* setup IVORs to match fixed offsets */
@@ -362,11 +404,20 @@ __secondary_start_page:
 	/* mask by ~64M to setup our tlb we will jump to */
 	rlwinm	r12,r4,0,0,5
 
-	/* setup r3, r4, r5, r6, r7, r8, r9 */
+	/*
+	 * setup r3, r4, r5, r6, r7, r8, r9
+	 * r3 contains the value to put in the r3 register at secondary cpu
+	 * entry. The high 32-bits are ignored on 32-bit chip implementations.
+	 * 64-bit chip implementations however shall load all 64-bits
+	 */
+#ifdef CONFIG_SYS_PPC64
+	ld	r3,ENTRY_R3_UPPER(r10)
+#else
 	lwz	r3,ENTRY_R3_LOWER(r10)
+#endif
 	li	r4,0
 	li	r5,0
-	lwz	r6,ENTRY_R6_LOWER(r10)
+	li	r6,0
 	lis	r7,(64*1024*1024)@h
 	li	r8,0
 	li	r9,0
@@ -404,32 +455,10 @@ __secondary_start_page:
 	mtspr	SPRN_SRR1,r13
 	rfi
 
-	/*
-	 * Allocate some space for the SDRAM address of the bootpg.
-	 * This variable has to be in the boot page so that it can
-	 * be accessed by secondary cores when they come out of reset.
-	 */
-	.globl __bootpg_addr
-__bootpg_addr:
-	.long	0
 
-	.align L1_CACHE_SHIFT
+	.align 6
 	.globl __spin_table
 __spin_table:
 	.space CONFIG_MAX_CPUS*ENTRY_SIZE
-
-	/*
-	 * This variable is set by cpu_init_r() after parsing hwconfig
-	 * to enable workaround for erratum NMG_CPU_A011.
-	 */
-	.align L1_CACHE_SHIFT
-	.global enable_cpu_a011_workaround
-enable_cpu_a011_workaround:
-	.long	1
-
-	/* Fill in the empty space.  The actual reset vector is
-	 * the last word of the page */
-__secondary_start_code_end:
-	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
-__secondary_reset_vector:
-	b	__secondary_start_page
+__spin_table_end:
+	.space 4096 - (__spin_table_end - __spin_table)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index abfeb26..801ee07 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -39,6 +39,10 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info (sys_info_t * sysInfo)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	u32 ccr;
+#endif
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
@@ -72,16 +76,22 @@ void get_sys_info (sys_info_t * sysInfo)
 		[13] = 2,	/* CC4 PPL / 2 */
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
-	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
-	uint ratio[4];
+	uint i, freqCC_PLL[6], rcw_tmp;
+	uint ratio[6];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	uint mem_pll_rat;
 
 	sysInfo->freqSystemBus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+	sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
+#else
 	sysInfo->freqDDRBus = sysclk;
+#endif
 
 	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
+			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
+			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 	if (mem_pll_rat > 2)
 		sysInfo->freqDDRBus *= mem_pll_rat;
 	else
@@ -91,27 +101,151 @@ void get_sys_info (sys_info_t * sysInfo)
 	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
 	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
 	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
-	for (i = 0; i < 4; i++) {
+	ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
+	ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
+	for (i = 0; i < 6; i++) {
 		if (ratio[i] > 4)
 			freqCC_PLL[i] = sysclk * ratio[i];
 		else
 			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
 	}
-	rcw_tmp = in_be32(&gur->rcwsr[3]);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	/*
+	 * Each cluster has up to 4 cores, sharing the same PLL selection.
+	 * The cluster assignment is fixed per SoC. There is no way identify the
+	 * assignment so far, presuming the "first configuration" which is to
+	 * fill the lower cluster group first before moving up to next group.
+	 * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
+	 * and core 4~7 on cluster 2
+	 * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
+	 * and core 12~15 on cluster 4 if existing
+	 */
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
-		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+		u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
+				& 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+		if (cplx_pll > 3)
+			printf("Unsupported architecture configuration"
+				" in function %s\n", __func__);
+		cplx_pll += (cpu / 8) * 3;
 
 		sysInfo->freqProcessor[cpu] =
 			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
 	}
+#define PME_CLK_SEL	0xe0000000
+#define PME_CLK_SHIFT	29
+#define FM1_CLK_SEL	0x1c000000
+#define FM1_CLK_SHIFT	26
+	rcw_tmp = in_be32(&gur->rcwsr[7]);
+
+#ifdef CONFIG_SYS_DPAA_PME
+	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
+	case 1:
+		sysInfo->freqPME = freqCC_PLL[0];
+		break;
+	case 2:
+		sysInfo->freqPME = freqCC_PLL[0] / 2;
+		break;
+	case 3:
+		sysInfo->freqPME = freqCC_PLL[0] / 3;
+		break;
+	case 4:
+		sysInfo->freqPME = freqCC_PLL[0] / 4;
+		break;
+	case 6:
+		sysInfo->freqPME = freqCC_PLL[1] / 2;
+		break;
+	case 7:
+		sysInfo->freqPME = freqCC_PLL[1] / 3;
+		break;
+	default:
+		printf("Error: Unknown PME clock select!\n");
+	case 0:
+		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+		break;
 
+	}
+#endif
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
+	case 1:
+		sysInfo->freqFMan[0] = freqCC_PLL[3];
+		break;
+	case 2:
+		sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
+		break;
+	case 3:
+		sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
+		break;
+	case 4:
+		sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
+		break;
+	case 6:
+		sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
+		break;
+	case 7:
+		sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
+		break;
+	default:
+		printf("Error: Unknown FMan1 clock select!\n");
+	case 0:
+		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+		break;
+	}
+#if (CONFIG_SYS_NUM_FMAN) == 2
+#define FM2_CLK_SEL	0x00000038
+#define FM2_CLK_SHIFT	3
+	rcw_tmp = in_be32(&gur->rcwsr[15]);
+	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
+	case 1:
+		sysInfo->freqFMan[1] = freqCC_PLL[4];
+		break;
+	case 2:
+		sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
+		break;
+	case 3:
+		sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
+		break;
+	case 4:
+		sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
+		break;
+	case 6:
+		sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
+		break;
+	case 7:
+		sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
+		break;
+	default:
+		printf("Error: Unknown FMan2 clock select!\n");
+	case 0:
+		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+		break;
+	}
+#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
+#endif	/* CONFIG_SYS_DPAA_FMAN */
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+
+		sysInfo->freqProcessor[cpu] =
+			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
+	}
 #define PME_CLK_SEL	0x80000000
 #define FM1_CLK_SEL	0x40000000
 #define FM2_CLK_SEL	0x20000000
 #define HWA_ASYNC_DIV	0x04000000
 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
 #define HWA_CC_PLL	1
+#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
+#define HWA_CC_PLL	2
 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
 #define HWA_CC_PLL	2
 #else
@@ -151,11 +285,10 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 #endif
 
-#else
-	uint plat_ratio,e500_ratio,half_freqSystemBus;
-#if defined(CONFIG_FSL_LBC)
-	uint lcrr_div;
-#endif
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#else /* CONFIG_FSL_CORENET */
+	uint plat_ratio, e500_ratio, half_freqSystemBus;
 	int i;
 #ifdef CONFIG_QE
 	__maybe_unused u32 qe_ratio;
@@ -202,6 +335,7 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif /* CONFIG_FSL_CORENET */
 
 #if defined(CONFIG_FSL_LBC)
+	uint lcrr_div;
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -228,6 +362,13 @@ void get_sys_info (sys_info_t * sysInfo)
 		sysInfo->freqLocalBus = lcrr_div;
 	}
 #endif
+
+#if defined(CONFIG_FSL_IFC)
+	ccr = in_be32(&ifc_regs->ifc_ccr);
+	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+	sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
+#endif
 }
 
 
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 9e04257..ac17f9d 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -169,7 +169,7 @@ l2_disabled:
 	 *
 	 */
 
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+#ifdef CONFIG_SYS_CACHE_STASHING
 	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
 	li	r2,(32 + 0)
 	mtspr	L1CSR2,r2
@@ -211,6 +211,77 @@ l2_disabled:
 	andi.	r1,r3,L1CSR0_DCE@l
 	beq	2b
 
+	.macro	create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
+	lis	\scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
+	mtspr	MAS0, \scratch
+	lis	\scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
+	mtspr	MAS1, \scratch
+	lis	\scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+	mtspr	MAS2, \scratch
+	lis	\scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
+	mtspr	MAS3, \scratch
+	lis	\scratch, \phy_high@h
+	ori	\scratch, \scratch, \phy_high@l
+	mtspr	MAS7, \scratch
+	isync
+	msync
+	tlbwe
+	isync
+	.endm
+
+	.macro	create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
+	lis	\scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
+	mtspr	MAS0, \scratch
+	lis	\scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
+	mtspr	MAS1, \scratch
+	lis	\scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+	mtspr	MAS2, \scratch
+	lis	\scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
+	mtspr	MAS3, \scratch
+	lis	\scratch, \phy_high@h
+	ori	\scratch, \scratch, \phy_high@l
+	mtspr	MAS7, \scratch
+	isync
+	msync
+	tlbwe
+	isync
+	.endm
+
+	.macro	delete_tlb1_entry esel scratch
+	lis	\scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
+	mtspr	MAS0, \scratch
+	li	\scratch, 0
+	mtspr	MAS1, \scratch
+	isync
+	msync
+	tlbwe
+	isync
+	.endm
+
+	.macro	delete_tlb0_entry esel epn wimg scratch
+	lis	\scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
+	mtspr	MAS0, \scratch
+	li	\scratch, 0
+	mtspr	MAS1, \scratch
+	lis	\scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+	mtspr	MAS2, \scratch
+	isync
+	msync
+	tlbwe
+	isync
+	.endm
+
 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
 /*
  * TLB entry for debuggging in AS1
@@ -220,61 +291,35 @@ l2_disabled:
  * in AS1.
  */
 
-	lis     r6,FSL_BOOKE_MAS0(1,
-			CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
-	ori     r6,r6,FSL_BOOKE_MAS0(1,
-			CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
-
 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
 /*
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
  * and this window is outside of 4K boot window.
  */
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
-							(MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
-							(MAS2_I|MAS2_G))@l
+	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+		0, BOOKE_PAGESZ_4M, \
+		CONFIG_SYS_MONITOR_BASE & 0xffc00000,  MAS2_I|MAS2_G, \
+		0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 
-	/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
-	lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
-
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+		0, BOOKE_PAGESZ_1M, \
+		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+		CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #else
 /*
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  * because "nexti" will resize TLB to 4K
  */
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
-							(MAS2_I))@l
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+		0, BOOKE_PAGESZ_256K, \
+		CONFIG_SYS_MONITOR_BASE, MAS2_I, \
+		CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #endif
-	mtspr   MAS0,r6
-	mtspr   MAS1,r7
-	mtspr   MAS2,r8
-	mtspr   MAS3,r9
-	tlbwe
-	isync
 #endif
 
 /*
@@ -392,27 +437,11 @@ l2_disabled:
 	 */
 
 	/* create a temp mapping TLB0[0] for LBCR  */
-	lis     r6,FSL_BOOKE_MAS0(0, 0, 0)@h
-	ori     r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
-
-	lis     r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
-
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@l
-
-	mtspr   MAS0,r6
-	mtspr   MAS1,r7
-	mtspr   MAS2,r8
-	mtspr   MAS3,r9
-	isync
-	msync
-	tlbwe
+	create_tlb0_entry 0, \
+		0, BOOKE_PAGESZ_4K, \
+		CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
+		CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
+		0, r6
 
 	/* Set LBCR register */
 	lis     r4,CONFIG_SYS_LBCR_ADDR@h
@@ -551,49 +580,22 @@ create_ccsr_new_tlb:
 	ori	r8, r8, CONFIG_SYS_CCSRBAR@l
 	lis	r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
 	ori	r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
-	lis     r0, FSL_BOOKE_MAS0(0, 0, 0)@h
-	ori     r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
-	lis     r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
-	ori     r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
-	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
-	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
-	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
-	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
-#ifdef CONFIG_ENABLE_36BIT_PHYS
-	lis	r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
-	ori	r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
-	mtspr   MAS7, r7
-#endif
-	mtspr   MAS0, r0
-	mtspr   MAS1, r1
-	mtspr   MAS2, r2
-	mtspr   MAS3, r3
-	isync
-	msync
-	tlbwe
-
+	create_tlb0_entry 0, \
+		0, BOOKE_PAGESZ_4K, \
+		CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
+		CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
+		CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
 	/*
 	 * Create a TLB for the current location of CCSR.  Register R9 is reserved
 	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
 	 */
 create_ccsr_old_tlb:
-	lis     r0, FSL_BOOKE_MAS0(0, 1, 0)@h
-	ori     r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
-	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
-	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
-	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
-	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
-#ifdef CONFIG_ENABLE_36BIT_PHYS
-	li	r7, 0	/* The default CCSR address is always a 32-bit number */
-	mtspr   MAS7, r7
-#endif
-	mtspr   MAS0, r0
-	/* MAS1 is the same as above */
-	mtspr   MAS2, r2
-	mtspr   MAS3, r3
-	isync
-	msync
-	tlbwe
+	create_tlb0_entry 1, \
+		0, BOOKE_PAGESZ_4K, \
+		CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
+		CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
+		0, r3 /* The default CCSR address is always a 32-bit number */
+
 
 	/*
 	 * We have a TLB for what we think is the current (old) CCSR.  Let's
@@ -743,29 +745,46 @@ write_new_ccsrbar:
 
 	/* Delete the temporary TLBs */
 delete_temp_tlbs:
-	lis     r0, FSL_BOOKE_MAS0(0, 0, 0)@h
-	ori     r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
-	li	r1, 0
-	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
-	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
-	mtspr   MAS0, r0
-	mtspr   MAS1, r1
-	mtspr   MAS2, r2
-	isync
-	msync
-	tlbwe
+	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
+	delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
 
-	lis     r0, FSL_BOOKE_MAS0(0, 1, 0)@h
-	ori     r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
-	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
-	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
-	mtspr   MAS0, r0
-	mtspr   MAS2, r2
-	isync
-	msync
-	tlbwe
 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+create_ccsr_l2_tlb:
+	/*
+	 * Create a TLB for the MMR location of CCSR
+	 * to access L2CSR0 register
+	 */
+	create_tlb0_entry 0, \
+		0, BOOKE_PAGESZ_4K, \
+		CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
+		CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
+		CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+
+enable_l2_cluster_l2:
+	/* enable L2 cache */
+	lis	r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
+	ori	r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
+	li	r4, 33	/* stash id */
+	stw	r4, 4(r3)
+	lis	r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
+	ori	r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
+	sync
+	stw	r4, 0(r3)	/* invalidate L2 */
+1:	sync
+	lwz	r0, 0(r3)
+	twi	0, r0, 0
+	isync
+	and.	r1, r0, r4
+	bne	1b
+	lis	r4, L2CSR0_L2E@h
+	sync
+	stw	r4, 0(r3)	/* eanble L2 */
+delete_ccsr_l2_tlb:
+	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 #define DCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
 #define LAW_SIZE_1M	0x13
@@ -1019,83 +1038,50 @@ create_init_ram_area:
 
 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
 	/* create a temp mapping in AS=1 to the 4M boot window */
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
+	create_tlb1_entry 15, \
+		1, BOOKE_PAGESZ_4M, \
+		CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
+		0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
-
-	/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
-	lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
 	/* create a temp mapping in AS = 1 for Flash mapping
 	 * created by PBL for ISBC code
 	*/
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
-
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry 15, \
+		1, BOOKE_PAGESZ_1M, \
+		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+		CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #else
 	/*
 	 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
 	 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
 	 */
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
-
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry 15, \
+		1, BOOKE_PAGESZ_1M, \
+		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+		CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #endif
 
-	mtspr   MAS0,r6
-	mtspr   MAS1,r7
-	mtspr   MAS2,r8
-	mtspr   MAS3,r9
-	isync
-	msync
-	tlbwe
-
 	/* create a temp mapping in AS=1 to the stack */
-	lis     r6,FSL_BOOKE_MAS0(1, 14, 0)@h
-	ori     r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
-
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
-
 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
     defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
-				(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
-				(MAS3_SX|MAS3_SW|MAS3_SR))@l
-	li      r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
-	mtspr	MAS7,r10
+	create_tlb1_entry 14, \
+		1, BOOKE_PAGESZ_16K, \
+		CONFIG_SYS_INIT_RAM_ADDR, 0, \
+		CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
+
 #else
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry 14, \
+		1, BOOKE_PAGESZ_16K, \
+		CONFIG_SYS_INIT_RAM_ADDR, 0, \
+		CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #endif
 
-	mtspr   MAS0,r6
-	mtspr   MAS1,r7
-	mtspr   MAS2,r8
-	mtspr   MAS3,r9
-	isync
-	msync
-	tlbwe
-
 	lis	r6,MSR_IS|MSR_DS|MSR_DE@h
 	ori	r6,r6,MSR_IS|MSR_DS|MSR_DE@l
 	lis	r7,switch_as@h
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
new file mode 100644
index 0000000..a8f16b1
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO(1, 27, 1, 0),
+	SET_QP_INFO(2, 28, 1, 0),
+	SET_QP_INFO(3, 29, 1, 1),
+	SET_QP_INFO(4, 30, 1, 1),
+	SET_QP_INFO(5, 31, 1, 2),
+	SET_QP_INFO(6, 32, 1, 2),
+	SET_QP_INFO(7, 33, 1, 3),
+	SET_QP_INFO(8, 34, 1, 3),
+	SET_QP_INFO(9, 35, 1, 4),
+	SET_QP_INFO(10, 36, 1, 4),
+	SET_QP_INFO(11, 37, 1, 5),
+	SET_QP_INFO(12, 38, 1, 5),
+	SET_QP_INFO(13, 39, 1, 6),
+	SET_QP_INFO(14, 40, 1, 6),
+	SET_QP_INFO(15, 41, 1, 7),
+	SET_QP_INFO(16, 42, 1, 7),
+	SET_QP_INFO(17, 43, 1, 8),
+	SET_QP_INFO(18, 44, 1, 8),
+	SET_QP_INFO(19, 45, 1, 9),
+	SET_QP_INFO(20, 46, 1, 9),
+	SET_QP_INFO(21, 47, 1, 10),
+	SET_QP_INFO(22, 48, 1, 10),
+	SET_QP_INFO(23, 49, 1, 11),
+	SET_QP_INFO(24, 50, 1, 11),
+	SET_QP_INFO(65, 89, 1, 0),
+	SET_QP_INFO(66, 90, 1, 0),
+	SET_QP_INFO(67, 91, 1, 1),
+	SET_QP_INFO(68, 92, 1, 1),
+	SET_QP_INFO(69, 93, 1, 2),
+	SET_QP_INFO(70, 94, 1, 2),
+	SET_QP_INFO(71, 95, 1, 3),
+	SET_QP_INFO(72, 96, 1, 3),
+	SET_QP_INFO(73, 97, 1, 4),
+	SET_QP_INFO(74, 98, 1, 4),
+	SET_QP_INFO(75, 99, 1, 5),
+	SET_QP_INFO(76, 100, 1, 5),
+	SET_QP_INFO(77, 101, 1, 6),
+	SET_QP_INFO(78, 102, 1, 6),
+	SET_QP_INFO(79, 103, 1, 7),
+	SET_QP_INFO(80, 104, 1, 7),
+	SET_QP_INFO(81, 105, 1, 8),
+	SET_QP_INFO(82, 106, 1, 8),
+	SET_QP_INFO(83, 107, 1, 9),
+	SET_QP_INFO(84, 108, 1, 9),
+	SET_QP_INFO(85, 109, 1, 10),
+	SET_QP_INFO(86, 110, 1, 10),
+	SET_QP_INFO(87, 111, 1, 11),
+	SET_QP_INFO(88, 112, 1, 11),
+	SET_QP_INFO(25, 51, 1, 0),
+	SET_QP_INFO(26, 52, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+	SET_SRIO_LIODN_1(1, 307),
+	SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(62),
+	SET_BMAN_LIODN(63),
+#endif
+
+	SET_SDHC_LIODN(1, 552),
+
+	SET_PME_LIODN(117),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+	SET_SATA_LIODN(1, 555),
+	SET_SATA_LIODN(2, 556),
+
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+
+	SET_DMA_LIODN(1, 147),
+	SET_DMA_LIODN(2, 227),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+#ifdef CONFIG_SYS_PMAN
+	SET_PMAN_LIODN(1, 513),
+	SET_PMAN_LIODN(2, 514),
+	SET_PMAN_LIODN(3, 515),
+#endif
+
+	/* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 88),
+	SET_FMAN_RX_1G_LIODN(1, 1, 89),
+	SET_FMAN_RX_1G_LIODN(1, 2, 90),
+	SET_FMAN_RX_1G_LIODN(1, 3, 91),
+	SET_FMAN_RX_1G_LIODN(1, 4, 92),
+	SET_FMAN_RX_1G_LIODN(1, 5, 93),
+	SET_FMAN_RX_10G_LIODN(1, 0, 94),
+	SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(2, 0, 88),
+	SET_FMAN_RX_1G_LIODN(2, 1, 89),
+	SET_FMAN_RX_1G_LIODN(2, 2, 90),
+	SET_FMAN_RX_1G_LIODN(2, 3, 91),
+	SET_FMAN_RX_1G_LIODN(2, 4, 92),
+	SET_FMAN_RX_1G_LIODN(2, 5, 93),
+	SET_FMAN_RX_10G_LIODN(2, 0, 94),
+	SET_FMAN_RX_10G_LIODN(2, 1, 95),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+	SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+	SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+	SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+	SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+	SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+	SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+	SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+	SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+	SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+	SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+	SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+	/* Set RMan block 0-3 liodn offset */
+	SET_RMAN_LIODN(0, 678),
+	SET_RMAN_LIODN(1, 679),
+	SET_RMAN_LIODN(2, 680),
+	SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+#ifdef CONFIG_SYS_DPAA_DCE
+	[FSL_HW_PORTAL_DCE]  = SET_LIODN_BASE_2(618, 694),
+#endif
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069),
+#endif
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(770, 846),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+	[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
new file mode 100644
index 0000000..102defa
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+	{4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC10, XAUI_FM2_MAC10,
+		XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
+	{2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+	{4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+	{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, XFI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, XFI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{}
+};
+static struct serdes_config serdes3_cfg_tbl[] = {
+	/* SerDes 3 */
+	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{}
+};
+static struct serdes_config serdes4_cfg_tbl[] = {
+	/* SerDes 4 */
+	{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+	{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}},
+	{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}},
+	{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+	{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+	{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
+	{}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+	serdes2_cfg_tbl,
+	serdes3_cfg_tbl,
+	serdes4_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 929f6a6..a548dec 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -249,7 +249,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 {
 	int i;
 	unsigned int tlb_size;
-	unsigned int wimge = 0;
+	unsigned int wimge = MAS2_M;
 	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
 	unsigned int max_cam;
 	u64 size, memsize = (u64)memsize_in_meg << 20;
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index 61f5110..2f955fe 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c
@@ -20,7 +20,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_MP
 	int off;
-	u32 bootpg = determine_mp_bootpg();
+	u32 bootpg = determine_mp_bootpg(NULL);
 #endif
 
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c
index 30c99eb..de705f0 100644
--- a/arch/powerpc/cpu/mpc86xx/mp.c
+++ b/arch/powerpc/cpu/mpc86xx/mp.c
@@ -90,8 +90,11 @@ int cpu_release(int nr, int argc, char * const argv[])
 	return 1;
 }
 
-u32 determine_mp_bootpg(void)
+u32 determine_mp_bootpg(unsigned int *pagesize)
 {
+	if (pagesize)
+		*pagesize = 4096;
+
 	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
 	if ((u64)gd->ram_size > 0xfffff000)
 		return (0xfff00000);
@@ -101,7 +104,7 @@ u32 determine_mp_bootpg(void)
 
 void cpu_mp_lmb_reserve(struct lmb *lmb)
 {
-	u32 bootpg = determine_mp_bootpg();
+	u32 bootpg = determine_mp_bootpg(NULL);
 
 	/* tell u-boot we stole a page */
 	lmb_reserve(lmb, bootpg, 4096);
@@ -115,7 +118,7 @@ void setup_mp(void)
 {
 	extern ulong __secondary_start_page;
 	ulong fixup = (ulong)&__secondary_start_page;
-	u32 bootpg = determine_mp_bootpg();
+	u32 bootpg = determine_mp_bootpg(NULL);
 	u32 bootpg_va;
 
 	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 78a8f92..2c487ca 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -73,6 +73,17 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(P4080, P4080, 8),
 	CPU_TYPE_ENTRY(P5010, P5010, 1),
 	CPU_TYPE_ENTRY(P5020, P5020, 2),
+	CPU_TYPE_ENTRY(P5021, P5021, 2),
+	CPU_TYPE_ENTRY(P5040, P5040, 4),
+	CPU_TYPE_ENTRY(T4240, T4240, 0),
+	CPU_TYPE_ENTRY(T4120, T4120, 0),
+	CPU_TYPE_ENTRY(B4860, B4860, 0),
+	CPU_TYPE_ENTRY(G4860, G4860, 0),
+	CPU_TYPE_ENTRY(G4060, G4060, 0),
+	CPU_TYPE_ENTRY(B4440, B4440, 0),
+	CPU_TYPE_ENTRY(G4440, G4440, 0),
+	CPU_TYPE_ENTRY(B4420, B4420, 0),
+	CPU_TYPE_ENTRY(B4220, B4220, 0),
 	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 #elif defined(CONFIG_MPC86xx)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 2592873..5928eb8 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -229,6 +229,26 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 
 #if !defined(CONFIG_FSL_DDR1)
+static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
+{
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
+	if (dimm_params[0].n_ranks == 4)
+		return 1;
+#endif
+
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
+	if ((dimm_params[0].n_ranks == 2) &&
+		(dimm_params[1].n_ranks == 2))
+		return 1;
+
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+	if (dimm_params[0].n_ranks == 4)
+		return 1;
+#endif
+#endif
+	return 0;
+}
+
 /*
  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
  *
@@ -236,7 +256,8 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
  * dreams up non-zero default values to be backwards compatible.
  */
 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
-				const memctl_options_t *popts)
+				const memctl_options_t *popts,
+				const dimm_params_t *dimm_params)
 {
 	unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 	unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
@@ -266,7 +287,18 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int data_rate = get_ddr_freq(0);
 	tmrd_mclk = 4;
 	/* set the turnaround time */
-	trwt_mclk = 1;
+
+	/*
+	 * for single quad-rank DIMM and two dual-rank DIMMs
+	 * to avoid ODT overlap
+	 */
+	if (avoid_odt_overlap(dimm_params)) {
+		twwt_mclk = 2;
+		trrt_mclk = 1;
+	}
+	/* for faster clock, need more time for data setup */
+	trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
+
 	if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 		twrt_mclk = 1;
 
@@ -451,8 +483,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 		| ((caslat_ctrl & 0xF) << 16)
 		| ((refrec_ctrl & 0xF) << 12)
 		| ((wrrec_mclk & 0x0F) << 8)
-		| ((acttoact_mclk & 0x07) << 4)
-		| ((wrtord_mclk & 0x07) << 0)
+		| ((acttoact_mclk & 0x0F) << 4)
+		| ((wrtord_mclk & 0x0F) << 0)
 		);
 	debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 }
@@ -659,6 +691,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int dqs_cfg;		/* DQS configuration */
 	unsigned int odt_cfg = 0;	/* ODT configuration */
 	unsigned int num_pr;		/* Number of posted refreshes */
+	unsigned int slow = 0;		/* DDR will be run less than 1250 */
 	unsigned int obc_cfg;		/* On-The-Fly Burst Chop Cfg */
 	unsigned int ap_en;		/* Address Parity Enable */
 	unsigned int d_init;		/* DRAM data initialization */
@@ -692,6 +725,10 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	obc_cfg = 0;
 #endif
 
+#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
+	slow = get_ddr_freq(0) < 1249000000;
+#endif
+
 	if (popts->registered_dimm_en) {
 		rcw_en = 1;
 		ap_en = popts->ap_en;
@@ -720,6 +757,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((dqs_cfg & 0x3) << 26)
 		| ((odt_cfg & 0x3) << 21)
 		| ((num_pr & 0xf) << 12)
+		| ((slow & 1) << 11)
 		| (qd_en << 9)
 		| (unq_mrs_en << 8)
 		| ((obc_cfg & 0x1) << 6)
@@ -1347,6 +1385,11 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
 			       | ((wrlvl_start & 0x1F) << 0)
 			       );
 	debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
+	ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
+	debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
+	ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
+	debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
+
 }
 
 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
@@ -1370,6 +1413,12 @@ static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
 	debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
 }
 
+static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+	ddr->ddr_cdr2 = popts->ddr_cdr2;
+	debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
+}
+
 unsigned int
 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 {
@@ -1466,7 +1515,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 				break;
 			}
 			sa = common_dimm->base_address;
-			ea = common_dimm->total_mem - 1;
+			ea = sa + common_dimm->total_mem - 1;
 		} else if (!popts->memctl_interleaving) {
 			/*
 			 * If memory interleaving between controllers is NOT
@@ -1480,7 +1529,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 			case FSL_DDR_CS0_CS1_CS2_CS3:
 				sa = common_dimm->base_address;
-				ea = common_dimm->total_mem - 1;
+				ea = sa + common_dimm->total_mem - 1;
 				break;
 			case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 				if ((i >= 2) && (dimm_number == 0)) {
@@ -1537,17 +1586,19 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 		sa >>= 24;
 		ea >>= 24;
 
-		ddr->cs[i].bnds = (0
-			| ((sa & 0xFFF) << 16)	/* starting address MSB */
-			| ((ea & 0xFFF) << 0)	/* ending address MSB */
-			);
+		if (cs_en) {
+			ddr->cs[i].bnds = (0
+				| ((sa & 0xFFF) << 16)/* starting address MSB */
+				| ((ea & 0xFFF) << 0)	/* ending address MSB */
+				);
+		} else {
+			debug("FSLDDR: setting bnds to 0 for inactive CS\n");
+			ddr->cs[i].bnds = 0;
+		}
 
 		debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
-		if (cs_en) {
-			set_csn_config(dimm_number, i, ddr, popts, dimm_params);
-			set_csn_config_2(i, ddr);
-		} else
-			debug("CS%d is disabled.\n", i);
+		set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+		set_csn_config_2(i, ddr);
 	}
 
 	/*
@@ -1560,7 +1611,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_ddr_eor(ddr, popts);
 
 #if !defined(CONFIG_FSL_DDR1)
-	set_timing_cfg_0(ddr, popts);
+	set_timing_cfg_0(ddr, popts, dimm_params);
 #endif
 
 	set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
@@ -1569,6 +1620,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 				cas_latency, additive_latency);
 
 	set_ddr_cdr1(ddr, popts);
+	set_ddr_cdr2(ddr, popts);
 	set_ddr_sdram_cfg(ddr, popts, common_dimm);
 	ip_rev = fsl_ddr_get_version();
 	if (ip_rev > 0x40400)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index f59d105..cb71f94 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -452,6 +452,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),
+		CTRL_OPTIONS(ddr_cdr1),
+		CTRL_OPTIONS(ddr_cdr2),
 		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
 		CTRL_OPTIONS(tFAW_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
@@ -518,6 +520,8 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 		CFG_REGS(timing_cfg_5),
 		CFG_REGS(ddr_zq_cntl),
 		CFG_REGS(ddr_wrlvl_cntl),
+		CFG_REGS(ddr_wrlvl_cntl_2),
+		CFG_REGS(ddr_wrlvl_cntl_3),
 		CFG_REGS(ddr_sr_cntr),
 		CFG_REGS(ddr_sdram_rcw_1),
 		CFG_REGS(ddr_sdram_rcw_2),
@@ -525,6 +529,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 		CFG_REGS(ddr_cdr2),
 		CFG_REGS(err_disable),
 		CFG_REGS(err_int_en),
+		CFG_REGS(ddr_eor),
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
 
@@ -584,6 +589,8 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 		CFG_REGS(timing_cfg_5),
 		CFG_REGS(ddr_zq_cntl),
 		CFG_REGS(ddr_wrlvl_cntl),
+		CFG_REGS(ddr_wrlvl_cntl_2),
+		CFG_REGS(ddr_wrlvl_cntl_3),
 		CFG_REGS(ddr_sr_cntr),
 		CFG_REGS(ddr_sdram_rcw_1),
 		CFG_REGS(ddr_sdram_rcw_2),
@@ -593,7 +600,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 		CFG_REGS(err_int_en),
 		CFG_REGS(ddr_sdram_rcw_2),
 		CFG_REGS(ddr_sdram_rcw_2),
-
+		CFG_REGS(ddr_eor),
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
 
@@ -689,6 +696,8 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),
+		CTRL_OPTIONS_HEX(ddr_cdr1),
+		CTRL_OPTIONS_HEX(ddr_cdr2),
 		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
 		CTRL_OPTIONS(tFAW_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
@@ -1597,6 +1606,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 			 * doesn't return
 			 */
 			do_reset(NULL, 0, 0, NULL);
+			printf("Reset didn't work\n");
 		}
 
 		if (strcmp(argv[0], "recompute") == 0) {
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 03a784c..6a1f4e4 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -76,7 +76,7 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 unsigned int
 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 				      common_timing_params_t *outpdimm,
-				      unsigned int number_of_dimms)
+				      const unsigned int number_of_dimms)
 {
 	unsigned int i, j;
 
@@ -126,13 +126,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 			temp1++;
 			continue;
 		}
+
+		/*
+		 * check if quad-rank DIMM is plugged if
+		 * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
+		 * Only the board with proper design is capable
+		 */
+#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 		if (dimm_params[i].n_ranks == 4 && \
 		  CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
 			printf("Found Quad-rank DIMM, not able to support.");
 			temp1++;
 			continue;
 		}
-
+#endif
 		/*
 		 * Find minimum tCKmax_ps to find fastest slow speed,
 		 * i.e., this is the slowest the whole system can go.
@@ -236,11 +243,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	if (outpdimm->all_DIMMs_registered)
 		for (j = 0; j < 16; j++) {
 			outpdimm->rcw[j] = dimm_params[0].rcw[j];
-			for (i = 1; i < number_of_dimms; i++)
+			for (i = 1; i < number_of_dimms; i++) {
+				if (!dimm_params[i].n_ranks)
+					continue;
 				if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
 					temp1 = 1;
 					break;
 				}
+			}
 		}
 
 	if (temp1 != 0)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index b47268c..d6b73c7 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -77,7 +77,19 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
 				sizeof(generic_spd_eeprom_t));
 
 	if (ret) {
-		printf("DDR: failed to read SPD from address %u\n", i2c_address);
+		if (i2c_address ==
+#ifdef SPD_EEPROM_ADDRESS
+				SPD_EEPROM_ADDRESS
+#elif defined(SPD_EEPROM_ADDRESS1)
+				SPD_EEPROM_ADDRESS1
+#endif
+				) {
+			printf("DDR: failed to read SPD from address %u\n",
+				i2c_address);
+		} else {
+			debug("DDR: failed to read SPD from address %u\n",
+				i2c_address);
+		}
 		memset(spd, 0, sizeof(generic_spd_eeprom_t));
 	}
 }
@@ -526,6 +538,17 @@ phys_size_t fsl_ddr_sdram(void)
 #endif
 		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 
+	/* setup 3-way interleaving before enabling DDRC */
+	switch (info.memctl_opts[0].memctl_interleaving_mode) {
+	case FSL_DDR_3WAY_1KB_INTERLEAVING:
+	case FSL_DDR_3WAY_4KB_INTERLEAVING:
+	case FSL_DDR_3WAY_8KB_INTERLEAVING:
+		fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode);
+		break;
+	default:
+		break;
+	}
+
 	/* Program configuration registers. */
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 		debug("Programming controller %u\n", i);
@@ -561,7 +584,6 @@ phys_size_t fsl_ddr_sdram(void)
 			case FSL_DDR_3WAY_8KB_INTERLEAVING:
 				law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 				if (i == 0) {
-					fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode);
 					fsl_ddr_set_lawbar(&info.common_timing_params[i],
 						law_memctl, i);
 				}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 13e4825..2f13b8f 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -474,6 +474,34 @@ static const struct dynamic_odt odt_unknown[4] = {
 	}
 };
 #endif
+
+/*
+ * Automatically seleect bank interleaving mode based on DIMMs
+ * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
+ * This function only deal with one or two slots per controller.
+ */
+static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
+{
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+	if (pdimm[0].n_ranks == 4)
+		return FSL_DDR_CS0_CS1_CS2_CS3;
+	else if (pdimm[0].n_ranks == 2)
+		return FSL_DDR_CS0_CS1;
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+	if (pdimm[0].n_ranks == 4)
+		return FSL_DDR_CS0_CS1_CS2_CS3;
+#endif
+	if (pdimm[0].n_ranks == 2) {
+		if (pdimm[1].n_ranks == 2)
+			return FSL_DDR_CS0_CS1_CS2_CS3;
+		else
+			return FSL_DDR_CS0_CS1;
+	}
+#endif
+	return 0;
+}
+
 unsigned int populate_memctl_options(int all_DIMMs_registered,
 			memctl_options_t *popts,
 			dimm_params_t *pdimm,
@@ -510,6 +538,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 		}
 	} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
 		switch (pdimm[0].n_ranks) {
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+		case 4:
+			pdodt = single_Q;
+			if (pdimm[1].n_ranks)
+				printf("Error: Quad- and Dual-rank DIMMs "
+					"cannot be used together\n");
+			break;
+#endif
 		case 2:
 			switch (pdimm[1].n_ranks) {
 			case 2:
@@ -900,6 +936,9 @@ done:
 		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 						 "cs0_cs1_cs2_cs3", buf))
 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
+		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+						"auto", buf))
+			popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
 		else
 			printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 		switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
@@ -912,6 +951,10 @@ done:
 					"interleaving disabled!\n", ctrl_num);
 			}
 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+			if (pdimm[0].n_ranks == 4)
+				break;
+#endif
 			if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
 				popts->ba_intlv_ctl = 0;
 				printf("Not enough bank(chip-select) for "
@@ -1063,7 +1106,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
 			break;
 		}
 		debug("%d of %d controllers are interleaving.\n", j, k);
-		if (j != k) {
+		if (j && (j != k)) {
 			for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 				pinfo->memctl_opts[i].memctl_interleaving = 0;
 			printf("Not all controllers have compatible "
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
index 664ad09..940ffff 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
@@ -121,6 +121,16 @@ void fsl_ddr_set_intl3r(const unsigned int granule_size)
 #endif
 }
 
+u32 fsl_ddr_get_intl3r(void)
+{
+	u32 val = 0;
+#ifdef CONFIG_E6500
+	u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
+	val = *mcintl3r;
+#endif
+	return val;
+}
+
 void board_add_ram_info(int use_default)
 {
 #if defined(CONFIG_MPC83xx)
@@ -140,6 +150,18 @@ void board_add_ram_info(int use_default)
 	uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
 	int cas_lat;
 
+#if CONFIG_NUM_DDR_CONTROLLERS >= 2
+	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+		ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+		sdram_cfg = in_be32(&ddr->sdram_cfg);
+	}
+#endif
+#if CONFIG_NUM_DDR_CONTROLLERS >= 3
+	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+		ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+		sdram_cfg = in_be32(&ddr->sdram_cfg);
+	}
+#endif
 	puts(" (DDR");
 	switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 		SDRAM_CFG_SDRAM_TYPE_SHIFT) {
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 32ab050..68db8e2 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -139,6 +139,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 	const char *phys[] = { "ulpi", "utmi" };
 	const char *mode = NULL;
 	const char *phy_type = NULL;
+	const char *dr_mode_type = NULL;
+	const char *dr_phy_type = NULL;
 	char usb1_defined = 0;
 	int usb_mode_off = -1;
 	int usb_phy_off = -1;
@@ -156,6 +158,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 					break;
 				}
 			}
+
 			for (j = 0; j < ARRAY_SIZE(phys); j++) {
 				if (hwconfig_subarg_cmp(str, "phy_type",
 						phys[j])) {
@@ -163,31 +166,46 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 					break;
 				}
 			}
-			if (mode_idx >= 0) {
-				usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
-					modes[mode_idx], NULL, usb_mode_off);
-				if (usb_mode_off < 0)
-					return;
-			}
-			if (phy_idx >= 0) {
-				usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
-					NULL, phys[phy_idx], usb_phy_off);
-				if (usb_phy_off < 0)
-					return;
-			}
+
+			dr_mode_type = modes[mode_idx];
+			dr_phy_type = phys[phy_idx];
+
+			/* use usb_dr_mode and usb_phy_type if
+			   usb1_defined = 0; these variables are to
+			   be deprecated */
 			if (!strcmp(str, "usb1"))
 				usb1_defined = 1;
-			if (mode_idx < 0 && phy_idx < 0)
+
+			if (mode_idx < 0 && phy_idx < 0) {
 				printf("WARNING: invalid phy or mode\n");
+				return;
+			}
 		}
+
+		usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+			dr_mode_type, NULL, usb_mode_off);
+
+		if (usb_mode_off < 0)
+			return;
+
+		usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+			NULL, dr_phy_type, usb_phy_off);
+
+		if (usb_phy_off < 0)
+			return;
 	}
+
 	if (!usb1_defined) {
 		int usb_off = -1;
 		mode = getenv("usb_dr_mode");
 		phy_type = getenv("usb_phy_type");
-		if (!mode && !phy_type)
-			return;
-		fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
+		if (mode || phy_type) {
+			printf("WARNING: usb_dr_mode and usb_phy_type "
+				"are to be deprecated soon. Use "
+				"hwconfig to set these values instead!!\n");
+			fdt_fixup_usb_mode_phy_type(blob, mode,
+				phy_type, usb_off);
+		}
 	}
 }
 #endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 0cb65b3..6e6f7dc 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -22,7 +22,9 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
+#include <asm/errno.h>
 
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define SRIO_PORT_ACCEPT_ALL 0x10000001
 #define SRIO_IB_ATMU_AR 0x80f55000
 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -31,10 +33,16 @@
 #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
 #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
 #define SRIO_LCSBA1CSR 0x60000000
+#endif
 
 #if defined(CONFIG_FSL_CORENET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
+	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
+#else
 	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
 	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
+#endif
 	#define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
 	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
@@ -52,16 +60,206 @@
 #error "No defines for DEVDISR_SRIO"
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+/*
+ * Erratum A-004034
+ * Affects: SRIO
+ * Description: During port initialization, the SRIO port performs
+ * lane synchronization (detecting valid symbols on a lane) and
+ * lane alignment (coordinating multiple lanes to receive valid data
+ * across lanes). Internal errors in lane synchronization and lane
+ * alignment may cause failure to achieve link initialization at
+ * the configured port width.
+ * An SRIO port configured as a 4x port may see one of these scenarios:
+ * 1. One or more lanes fails to achieve lane synchronization. Depending
+ * on which lanes fail, this may result in downtraining from 4x to 1x
+ * on lane 0, 4x to 1x on lane R (redundant lane).
+ * 2. The link may fail to achieve lane alignment as a 4x, even though
+ * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
+ * An SRIO port configured as a 1x port may fail to complete port
+ * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
+ * Impact: SRIO port may downtrain to 1x, or may fail to complete
+ * link initialization. Once a port completes link initialization
+ * successfully, it will operate normally.
+ */
+static int srio_erratum_a004034(u8 port)
+{
+	serdes_corenet_t *srds_regs;
+	u32 conf_lane;
+	u32 init_lane;
+	int idx, first, last;
+	u32 i;
+	unsigned long long end_tick;
+	struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+	srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+	conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
+			>> (12 - port * 4)) & 0x3;
+	init_lane = (in_be32((void *)&srio_regs->lp_serial
+			.port[port].pccsr) >> 27) & 0x7;
+
+	/*
+	 * Start a counter set to ~2 ms after the SERDES reset is
+	 * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
+	 * corresponding to the SERDES bank/PLL for the SRIO port).
+	 */
+	 if (in_be32((void *)&srds_regs->bank[0].rstctl)
+		& SRDS_RSTCTL_RSTDONE) {
+		/*
+		 * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
+		 * PO=1 or the counter expires. If the counter expires, the
+		 * port has failed initialization: go to recover steps. If PO=1
+		 * and the desired port width is 1x, go to normal steps. If
+		 * PO = 1 and the desired port width is 4x, go to recover steps.
+		 */
+		end_tick = usec2ticks(2000) + get_ticks();
+		do {
+			if (in_be32((void *)&srio_regs->lp_serial
+				.port[port].pescsr) & 0x2) {
+				if (conf_lane == 0x1)
+					goto host_ok;
+				else {
+					if (init_lane == 0x2)
+						goto host_ok;
+					else
+						break;
+				}
+			}
+		} while (end_tick > get_ticks());
+
+		/* recover at most 3 times */
+		for (i = 0; i < 3; i++) {
+			/* Set SRIO PnCCSR[PD]=1 */
+			setbits_be32((void *)&srio_regs->lp_serial
+					.port[port].pccsr,
+					0x800000);
+			/*
+			* Set SRIO PnPCR[OBDEN] on the host to
+			* enable the discarding of any pending packets.
+			*/
+			setbits_be32((void *)&srio_regs->impl.port[port].pcr,
+				0x04);
+			/* Wait 50 us */
+			udelay(50);
+			/* Run sync command */
+			isync();
+
+			if (port)
+				first = serdes_get_first_lane(SRIO2);
+			else
+				first = serdes_get_first_lane(SRIO1);
+			if (unlikely(first < 0))
+				return -ENODEV;
+			if (conf_lane == 0x1)
+				last = first;
+			else
+				last = first + 3;
+			/*
+			 * Set SERDES BnGCRm0[RRST]=0 for each SRIO
+			 * bank n and lane m.
+			 */
+			for (idx = first; idx <= last; idx++)
+				clrbits_be32(&srds_regs->lane[idx].gcr0,
+				SRDS_GCR0_RRST);
+			/*
+			 * Read SERDES BnGCRm0 for each SRIO
+			 * bank n and lane m
+			 */
+			for (idx = first; idx <= last; idx++)
+				in_be32(&srds_regs->lane[idx].gcr0);
+			/* Run sync command */
+			isync();
+			/* Wait >= 100 ns */
+			udelay(1);
+			/*
+			 * Set SERDES BnGCRm0[RRST]=1 for each SRIO
+			 * bank n and lane m.
+			 */
+			for (idx = first; idx <= last; idx++)
+				setbits_be32(&srds_regs->lane[idx].gcr0,
+				SRDS_GCR0_RRST);
+			/*
+			 * Read SERDES BnGCRm0 for each SRIO
+			 * bank n and lane m
+			 */
+			for (idx = first; idx <= last; idx++)
+				in_be32(&srds_regs->lane[idx].gcr0);
+			/* Run sync command */
+			isync();
+			/* Wait >= 300 ns */
+			udelay(1);
+
+			/* Write 1 to clear all bits in SRIO PnSLCSR */
+			out_be32((void *)&srio_regs->impl.port[port].slcsr,
+				0xffffffff);
+			/* Clear SRIO PnPCR[OBDEN] on the host */
+			clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
+				0x04);
+			/* Set SRIO PnCCSR[PD]=0 */
+			clrbits_be32((void *)&srio_regs->lp_serial
+				.port[port].pccsr,
+				0x800000);
+			/* Wait >= 24 ms */
+			udelay(24000);
+			/* Poll the state of the port again */
+			init_lane =
+				(in_be32((void *)&srio_regs->lp_serial
+					.port[port].pccsr) >> 27) & 0x7;
+			if (in_be32((void *)&srio_regs->lp_serial
+				.port[port].pescsr) & 0x2) {
+				if (conf_lane == 0x1)
+					goto host_ok;
+				else {
+					if (init_lane == 0x2)
+						goto host_ok;
+				}
+			}
+			if (i == 2)
+				return -ENODEV;
+		}
+	} else
+		return -ENODEV;
+
+host_ok:
+	/* Poll PnESCSR[OES] on the host until it is clear */
+	end_tick = usec2ticks(1000000) + get_ticks();
+	do {
+		if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
+			& 0x10000)) {
+			out_be32(((void *)&srio_regs->lp_serial
+				.port[port].pescsr), 0xffffffff);
+			out_be32(((void *)&srio_regs->phys_err
+				.port[port].edcsr), 0);
+			out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
+			return 0;
+		}
+	} while (end_tick > get_ticks());
+
+	return -ENODEV;
+}
+#endif
+
 void srio_init(void)
 {
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
 	int srio1_used = 0, srio2_used = 0;
+	u32 *devdisr;
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	devdisr = &gur->devdisr3;
+#else
+	devdisr = &gur->devdisr;
+#endif
 	if (is_serdes_configured(SRIO1)) {
 		set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
 				law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
 				LAW_TRGT_IF_RIO_1);
 		srio1_used = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+		if (srio_erratum_a004034(0) < 0)
+			printf("SRIO1: enabled but port error\n");
+		else
+#endif
 		printf("SRIO1: enabled\n");
 	} else {
 		printf("SRIO1: disabled\n");
@@ -73,7 +271,13 @@ void srio_init(void)
 				law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
 				LAW_TRGT_IF_RIO_2);
 		srio2_used = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+		if (srio_erratum_a004034(1) < 0)
+			printf("SRIO2: enabled but port error\n");
+		else
+#endif
 		printf("SRIO2: enabled\n");
+
 	} else {
 		printf("SRIO2: disabled\n");
 	}
@@ -82,20 +286,20 @@ void srio_init(void)
 #ifdef CONFIG_FSL_CORENET
 	/* On FSL_CORENET devices we can disable individual ports */
 	if (!srio1_used)
-		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
+		setbits_be32(devdisr, _DEVDISR_SRIO1);
 	if (!srio2_used)
-		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
+		setbits_be32(devdisr, _DEVDISR_SRIO2);
 #endif
 
 	/* neither port is used - disable everything */
 	if (!srio1_used && !srio2_used) {
-		setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
-		setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
-		setbits_be32(&gur->devdisr, _DEVDISR_RMU);
+		setbits_be32(devdisr, _DEVDISR_SRIO1);
+		setbits_be32(devdisr, _DEVDISR_SRIO2);
+		setbits_be32(devdisr, _DEVDISR_RMU);
 	}
 }
 
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 void srio_boot_master(int port)
 {
 	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index aa27741..03baaee 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -27,6 +27,8 @@
 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
 #endif
 
+#define FSL_DDR_VER_4_7	47
+
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
 #define CONFIG_SYS_NUM_TLBCAMS		64
@@ -311,6 +313,7 @@
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
@@ -331,6 +334,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -338,8 +342,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2	0x11
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 
 #elif defined(CONFIG_PPC_P3041)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
@@ -360,6 +366,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -367,8 +374,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2	0x11
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			8
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_NUM_LAWS		32
@@ -389,7 +398,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -398,6 +407,7 @@
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -406,8 +416,11 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x20
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
+#define CONFIG_SYS_PPC64		/* 64-bit core */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
@@ -426,12 +439,43 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+
+#elif defined(CONFIG_PPC_P5040)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	3
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_NUM_FM2_DTSEC	5
+#define CONFIG_SYS_NUM_FM2_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_USB138
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_ERRATUM_A004699
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+#define CONFIG_SYS_FSL_ERRATUM_A004510
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS			1
@@ -445,6 +489,63 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+#elif defined(CONFIG_PPC_T4240)
+#define CONFIG_SYS_PPC64		/* 64-bit core */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#define CONFIG_MAX_CPUS			12
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	5
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SRDS_3
+#define CONFIG_SYS_FSL_SRDS_4
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	8
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#define CONFIG_SYS_NUM_FM2_DTSEC	8
+#define CONFIG_SYS_NUM_FM2_10GEC	2
+#define CONFIG_NUM_DDR_CONTROLLERS	3
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A004468
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+
+#elif defined(CONFIG_PPC_B4860)
+#define CONFIG_SYS_PPC64		/* 64-bit core */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	6
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+
 #else
 #error Processor type not defined for this platform
 #endif
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index e271342..640d329 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -84,6 +84,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define FSL_DDR_4WAY_4KB_INTERLEAVING	0x1C
 #define FSL_DDR_4WAY_8KB_INTERLEAVING	0x1D
 
+#define SDRAM_CS_CONFIG_EN		0x80000000
+
 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  */
 #define SDRAM_CFG_MEM_EN		0x80000000
@@ -96,6 +98,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
 #define SDRAM_CFG_DYN_PWR		0x00200000
 #define SDRAM_CFG_DBW_MASK		0x00180000
+#define SDRAM_CFG_DBW_SHIFT		19
 #define SDRAM_CFG_32_BE			0x00080000
 #define SDRAM_CFG_16_BE			0x00100000
 #define SDRAM_CFG_8_BE			0x00040000
@@ -145,6 +148,31 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 
 /* DDR_CDR1 */
 #define DDR_CDR1_DHC_EN	0x80000000
+#define DDR_CDR1_ODT_SHIFT	17
+#define DDR_CDR1_ODT_MASK	0x6
+#define DDR_CDR2_ODT_MASK	0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+
+#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
+	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#define DDR_CDR_ODT_OFF		0x0
+#define DDR_CDR_ODT_120ohm	0x1
+#define DDR_CDR_ODT_180ohm	0x2
+#define DDR_CDR_ODT_75ohm	0x3
+#define DDR_CDR_ODT_110ohm	0x4
+#define DDR_CDR_ODT_60hm	0x5
+#define DDR_CDR_ODT_70ohm	0x6
+#define DDR_CDR_ODT_47ohm	0x7
+#else
+#define DDR_CDR_ODT_75ohm	0x0
+#define DDR_CDR_ODT_55ohm	0x1
+#define DDR_CDR_ODT_60ohm	0x2
+#define DDR_CDR_ODT_50ohm	0x3
+#define DDR_CDR_ODT_150ohm	0x4
+#define DDR_CDR_ODT_43ohm	0x5
+#define DDR_CDR_ODT_120ohm	0x6
+#endif
 
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
@@ -177,6 +205,8 @@ typedef struct fsl_ddr_cfg_regs_s {
 	unsigned int timing_cfg_5;
 	unsigned int ddr_zq_cntl;
 	unsigned int ddr_wrlvl_cntl;
+	unsigned int ddr_wrlvl_cntl_2;
+	unsigned int ddr_wrlvl_cntl_3;
 	unsigned int ddr_sr_cntr;
 	unsigned int ddr_sdram_rcw_1;
 	unsigned int ddr_sdram_rcw_2;
@@ -262,6 +292,8 @@ typedef struct memctl_options_s {
 	unsigned int wrlvl_override;
 	unsigned int wrlvl_sample;		/* Write leveling */
 	unsigned int wrlvl_start;
+	unsigned int wrlvl_ctl_2;
+	unsigned int wrlvl_ctl_3;
 
 	unsigned int half_strength_driver_enable;
 	unsigned int twoT_en;
@@ -288,6 +320,7 @@ typedef struct memctl_options_s {
 	unsigned int rcw_2;
 	/* control register 1 */
 	unsigned int ddr_cdr1;
+	unsigned int ddr_cdr2;
 
 	unsigned int trwt_override;
 	unsigned int trwt;			/* read-to-write turnaround */
@@ -298,6 +331,7 @@ extern phys_size_t fsl_ddr_sdram_size(void);
 extern int fsl_use_spd(void);
 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 					unsigned int ctrl_num);
+u32 fsl_ddr_get_intl3r(void);
 
 /*
  * The 85xx boards have a common prototype for fixed_sdram so put the
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h
index 2c0c9bc..299daca 100644
--- a/arch/powerpc/include/asm/fsl_fman.h
+++ b/arch/powerpc/include/asm/fsl_fman.h
@@ -423,6 +423,14 @@ typedef struct fm_10gec_mdio {
 	u8	res[4*1024];
 } fm_10gec_mdio_t;
 
+typedef struct fm_memac {
+	u8	res[4*1024];
+} fm_memac_t;
+
+typedef struct fm_memac_mdio {
+	u8	res[4*1024];
+} fm_memac_mdio_t;
+
 typedef struct fm_1588 {
 	u8	res[4*1024];
 } fm_1588_t;
@@ -446,6 +454,14 @@ typedef struct ccsr_fman {
 	u8			res1[8*1024];
 	fm_soft_parser_t	fm_soft_parser;
 	u8			res2[96*1024];
+#ifdef CONFIG_SYS_FMAN_V3
+	struct {
+		fm_memac_t		fm_memac;
+		fm_memac_mdio_t		fm_memac_mdio;
+	} memac[10];
+	u8			res4[32*1024];
+	fm_memac_mdio_t		fm_dedicated_mdio[2];
+#else
 	struct {
 		fm_dtsec_t	fm_dtesc;
 		fm_mdio_t	fm_mdio;
@@ -455,6 +471,7 @@ typedef struct ccsr_fman {
 		fm_10gec_mdio_t		fm_10gec_mdio;
 	} mac_10g[1];
 	u8			res4[48*1024];
+#endif
 	fm_1588_t		fm_1588;
 	u8			res5[4*1024];
 } ccsr_fman_t;
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index a9973b8..d759de9 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -94,6 +94,11 @@ extern void fdt_fixup_liodn(void *blob);
 	SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
 		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+	SET_LIODN_ENTRY_1(compat, liodn,\
+		offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
 /* reg nodes for DMA start @ 0x300 */
 #define SET_DMA_LIODN(dmaNum, liodn) \
 	SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
@@ -118,6 +123,12 @@ extern void fdt_fixup_liodn(void *blob);
 		CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
 		CONFIG_SYS_FSL_CORENET_PME_OFFSET)
 
+#define SET_PMAN_LIODN(num, liodn) \
+	SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
+		offsetof(struct ccsr_pman, ppa1) + \
+		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+
 /* -1 from portID due to how immap has the registers */
 #define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
 	CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
@@ -184,11 +195,13 @@ extern void fdt_fixup_liodn(void *blob);
 extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
 extern struct liodn_id_table raide_liodn_tbl[];
 extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
+#ifdef CONFIG_SYS_SRIO
 extern struct srio_liodn_id_table srio_liodn_tbl[];
+extern int srio_liodn_tbl_sz;
+#endif
 extern struct liodn_id_table rman_liodn_tbl[];
 extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
 extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
-extern int srio_liodn_tbl_sz;
 extern int rman_liodn_tbl_sz;
 
 #endif
diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h
new file mode 100644
index 0000000..d6b60e6
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_memac.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *	Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MEMAC_H__
+#define __MEMAC_H__
+
+#include <phy.h>
+
+struct memac {
+	/* memac general control and status registers */
+	u32	res_0[2];
+	u32	command_config;	/* Control and configuration register */
+	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
+	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
+	u32	maxfrm;		/* Maximum frame length register */
+	u32	res_18[5];
+	u32	hashtable_ctrl;	/* Hash table control register */
+	u32	res_30[4];
+	u32	ievent;		/* Interrupt event register */
+	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
+	u32	res_48;
+	u32	imask;		/* interrupt mask register */
+	u32	res_50;
+	u32	cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
+	u32	cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
+	u32	rx_pause_status;	/* Receive pause status register */
+	u32	res_78[2];
+	u32	mac_addr[14];	/* MAC address */
+	u32	lpwake_timer;	/* EEE low power wakeup timer register */
+	u32	sleep_timer;	/* Transmit EEE Low Power Timer register */
+	u32	res_c0[8];
+	u32	statn_config;	/* Statistics configuration register */
+	u32	res_e4[7];
+
+	/* memac statistics counter registers */
+	u32	rx_eoct_l;	/* Rx ethernet octests lower */
+	u32	rx_eoct_u;	/* Rx ethernet octests upper */
+	u32	rx_oct_l;	/* Rx octests lower */
+	u32	rx_oct_u;	/* Rx octests upper */
+	u32	rx_align_err_l;	/* Rx alignment error lower */
+	u32	rx_align_err_u;	/* Rx alignment error upper */
+	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
+	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
+	u32	rx_frame_l;	/* Rx frame counter lower */
+	u32	rx_frame_u;	/* Rx frame counter upper */
+	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
+	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
+	u32	rx_vlan_l;	/* Rx VLAN frame lower */
+	u32	rx_vlan_u;	/* Rx VLAN frame upper */
+	u32	rx_err_l;	/* Rx frame error lower */
+	u32	rx_err_u;	/* Rx frame error upper */
+	u32	rx_uni_l;	/* Rx unicast frame lower */
+	u32	rx_uni_u;	/* Rx unicast frame upper */
+	u32	rx_multi_l;	/* Rx multicast frame lower */
+	u32	rx_multi_u;	/* Rx multicast frame upper */
+	u32	rx_brd_l;	/* Rx broadcast frame lower */
+	u32	rx_brd_u;	/* Rx broadcast frame upper */
+	u32	rx_drop_l;	/* Rx dropped packets lower */
+	u32	rx_drop_u;	/* Rx dropped packets upper */
+	u32	rx_pkt_l;	/* Rx packets lower */
+	u32	rx_pkt_u;	/* Rx packets upper */
+	u32	rx_undsz_l;	/* Rx undersized packet lower */
+	u32	rx_undsz_u;	/* Rx undersized packet upper */
+	u32	rx_64_l;	/* Rx 64 oct packet lower */
+	u32	rx_64_u;	/* Rx 64 oct packet upper */
+	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
+	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
+	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
+	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
+	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
+	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
+	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
+	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
+	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
+	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
+	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
+	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
+	u32	rx_oversz_l;	/* Rx oversized packet lower */
+	u32	rx_oversz_u;	/* Rx oversized packet upper */
+	u32	rx_jabber_l;	/* Rx Jabber packet lower */
+	u32	rx_jabber_u;	/* Rx Jabber packet upper */
+	u32	rx_frag_l;	/* Rx Fragment packet lower */
+	u32	rx_frag_u;	/* Rx Fragment packet upper */
+	u32	rx_cnp_l;	/* Rx control packet lower */
+	u32	rx_cnp_u;	/* Rx control packet upper */
+	u32	rx_drntp_l;	/* Rx dripped not truncated packet lower */
+	u32	rx_drntp_u;	/* Rx dripped not truncated packet upper */
+	u32	res_1d0[0xc];
+
+	u32	tx_eoct_l;	/* Tx ethernet octests lower */
+	u32	tx_eoct_u;	/* Tx ethernet octests upper */
+	u32	tx_oct_l;	/* Tx octests lower */
+	u32	tx_oct_u;	/* Tx octests upper */
+	u32	res_210[0x2];
+	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
+	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
+	u32	tx_frame_l;	/* Tx frame counter lower */
+	u32	tx_frame_u;	/* Tx frame counter upper */
+	u32	tx_frame_crc_err_l; /* Tx frame check sequence error lower */
+	u32	tx_frame_crc_err_u; /* Tx frame check sequence error upper */
+	u32	tx_vlan_l;	/* Tx VLAN frame lower */
+	u32	tx_vlan_u;	/* Tx VLAN frame upper */
+	u32	tx_frame_err_l;	/* Tx frame error lower */
+	u32	tx_frame_err_u;	/* Tx frame error upper */
+	u32	tx_uni_l;	/* Tx unicast frame lower */
+	u32	tx_uni_u;	/* Tx unicast frame upper */
+	u32	tx_multi_l;	/* Tx multicast frame lower */
+	u32	tx_multi_u;	/* Tx multicast frame upper */
+	u32	tx_brd_l;	/* Tx broadcast frame lower */
+	u32	tx_brd_u;	/* Tx broadcast frame upper */
+	u32	res_258[0x2];
+	u32	tx_pkt_l;	/* Tx packets lower */
+	u32	tx_pkt_u;	/* Tx packets upper */
+	u32	tx_undsz_l;	/* Tx undersized packet lower */
+	u32	tx_undsz_u;	/* Tx undersized packet upper */
+	u32	tx_64_l;	/* Tx 64 oct packet lower */
+	u32	tx_64_u;	/* Tx 64 oct packet upper */
+	u32	tx_127_l;	/* Tx 65 to 127 oct packet lower */
+	u32	tx_127_u;	/* Tx 65 to 127 oct packet upper */
+	u32	tx_255_l;	/* Tx 128 to 255 oct packet lower */
+	u32	tx_255_u;	/* Tx 128 to 255 oct packet upper */
+	u32	tx_511_l;	/* Tx 256 to 511 oct packet lower */
+	u32	tx_511_u;	/* Tx 256 to 511 oct packet upper */
+	u32	tx_1023_l;	/* Tx 512 to 1023 oct packet lower */
+	u32	tx_1023_u;	/* Tx 512 to 1023 oct packet upper */
+	u32	tx_1518_l;	/* Tx 1024 to 1518 oct packet lower */
+	u32	tx_1518_u;	/* Tx 1024 to 1518 oct packet upper */
+	u32	tx_1519_l;	/* Tx 1519 to max oct packet lower */
+	u32	tx_1519_u;	/* Tx 1519 to max oct packet upper */
+	u32	res_2a8[0x6];
+	u32	tx_cnp_l;	/* Tx control packet lower */
+	u32	tx_cnp_u;	/* Tx control packet upper */
+	u32	res_2c8[0xe];
+
+	/* Line interface control register */
+	u32 if_mode;		/* interface mode control */
+	u32 if_status;		/* interface status */
+	u32 res_308[0xe];
+
+	/* HiGig/2 Register */
+	u32 hg_config;	/* HiGig2 control and configuration */
+	u32 res_344[0x3];
+	u32 hg_pause_quanta;	/* HiGig2 pause quanta */
+	u32 res_354[0x3];
+	u32 hg_pause_thresh;	/* HiGig2 pause quanta threshold */
+	u32 res_364[0x3];
+	u32 hgrx_pause_status;	/* HiGig2 rx pause quanta status */
+	u32 hg_fifos_status;	/* HiGig2 fifos status */
+	u32 rhm;	/* Rx HiGig2 message counter register */
+	u32 thm;/* Tx HiGig2 message counter register */
+	u32 res_380[0x320];
+};
+
+/* COMMAND_CONFIG - command and configuration register */
+#define MEMAC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
+#define MEMAC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
+#define MEMAC_CMD_CFG_RXTX_EN	(MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
+
+/* HASHTABLE_CTRL - Hashtable control register */
+#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
+#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
+
+/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
+#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
+
+/* IMASK - interrupt mask register */
+#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
+#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
+#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
+#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
+#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
+#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
+#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
+#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
+#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
+#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
+#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
+#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
+#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
+#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
+#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
+#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
+
+#define IMASK_MASK_ALL		0x00000000
+
+/* IEVENT - interrupt event register */
+#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
+#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
+#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
+#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
+#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
+#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
+#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
+#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
+#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
+#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
+#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
+#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
+#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
+#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
+#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
+#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
+
+#define IEVENT_CLEAR_ALL	0xffffffff
+
+/* IF_MODE - Interface Mode Register */
+#define IF_MODE_EN_AUTO	0x00008000 /* 1 - Enable automatic speed selection */
+#define IF_MODE_XGMII	0x00000000 /* 00- XGMII(10) interface mode */
+#define IF_MODE_GMII		0x00000002 /* 10- GMII interface mode */
+#define IF_MODE_MASK	0x00000003 /* mask for mode interface mode */
+#define IF_MODE_RG		0x00000004 /* 1- RGMII */
+#define IF_MODE_RM		0x00000008 /* 1- RGMII */
+
+#define IF_DEFAULT	(IF_GMII)
+
+/* Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET      0x8000
+#define PHY_SGMII_CR_RESET_AN       0x0200
+#define PHY_SGMII_CR_DEF_VAL        0x1140
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_IF_MODE_AN        0x0002
+#define PHY_SGMII_IF_MODE_SGMII     0x0001
+
+struct memac_mdio_controller {
+	u32	res0[0xc];
+	u32	mdio_stat;	/* MDIO configuration and status */
+	u32	mdio_ctl;	/* MDIO control */
+	u32	mdio_data;	/* MDIO data */
+	u32	mdio_addr;	/* MDIO address */
+};
+
+#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
+#define MDIO_STAT_BSY		(1 << 0)
+#define MDIO_STAT_RD_ER		(1 << 1)
+#define MDIO_STAT_PRE		(1 << 5)
+#define MDIO_STAT_ENC		(1 << 6)
+#define MDIO_STAT_HOLD_15_CLK	(7 << 2)
+
+#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
+#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
+#define MDIO_CTL_PRE_DIS	(1 << 10)
+#define MDIO_CTL_SCAN_EN	(1 << 11)
+#define MDIO_CTL_POST_INC	(1 << 14)
+#define MDIO_CTL_READ		(1 << 15)
+
+#define MDIO_DATA(x)		(x & 0xffff)
+#define MDIO_DATA_BSY		(1 << 31)
+
+struct fsl_enet_mac;
+
+void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs,
+		int max_rx_len);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index 5644044..b75f5b9 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -32,15 +32,16 @@ enum fsl_dpaa_dev {
 	FSL_HW_PORTAL_FMAN2,
 #endif
 #endif
-#ifdef CONFIG_SYS_DPAA_PME
 	FSL_HW_PORTAL_PME,
-#endif
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 	FSL_HW_PORTAL_RAID_ENGINE,
 #endif
 #ifdef CONFIG_SYS_DPAA_RMAN
 	FSL_HW_PORTAL_RMAN,
 #endif
+#ifdef CONFIG_SYS_DPAA_DCE
+	FSL_HW_PORTAL_DCE,
+#endif
 
 };
 
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 22525f1..6cd7379 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -37,11 +37,17 @@ enum srds_prtcl {
 	SGMII_FM1_DTSEC3,
 	SGMII_FM1_DTSEC4,
 	SGMII_FM1_DTSEC5,
+	SGMII_FM1_DTSEC6,
+	SGMII_FM1_DTSEC9,
+	SGMII_FM1_DTSEC10,
 	SGMII_FM2_DTSEC1,
 	SGMII_FM2_DTSEC2,
 	SGMII_FM2_DTSEC3,
 	SGMII_FM2_DTSEC4,
 	SGMII_FM2_DTSEC5,
+	SGMII_FM2_DTSEC6,
+	SGMII_FM2_DTSEC9,
+	SGMII_FM2_DTSEC10,
 	SGMII_TSEC1,
 	SGMII_TSEC2,
 	SGMII_TSEC3,
@@ -49,13 +55,49 @@ enum srds_prtcl {
 	XAUI_FM1,
 	XAUI_FM2,
 	AURORA,
+	CPRI1,
+	CPRI2,
+	CPRI3,
+	CPRI4,
+	CPRI5,
+	CPRI6,
+	CPRI7,
+	CPRI8,
+	XAUI_FM1_MAC9,
+	XAUI_FM1_MAC10,
+	XAUI_FM2_MAC9,
+	XAUI_FM2_MAC10,
+	HIGIG_FM1_MAC9,
+	HIGIG_FM1_MAC10,
+	HIGIG_FM2_MAC9,
+	HIGIG_FM2_MAC10,
+	QSGMII_FM1_A,		/* A indicates MACs 1-4 */
+	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
+	QSGMII_FM2_A,
+	QSGMII_FM2_B,
+	XFI_FM1_MAC9,
+	XFI_FM1_MAC10,
+	XFI_FM2_MAC9,
+	XFI_FM2_MAC10,
+	INTERLAKEN,
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+	FSL_SRDS_3  = 2,
+	FSL_SRDS_4  = 3,
 };
 
 int is_serdes_configured(enum srds_prtcl device);
 void fsl_serdes_init(void);
 
 #ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+#else
 int serdes_get_first_lane(enum srds_prtcl device);
+#endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
 void serdes_reset_rx(enum srds_prtcl device);
 #endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7de33a7..969f726 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -296,7 +296,9 @@ typedef struct ccsr_pcix {
 	u32	cfg_addr;	/* PCIX Configuration Addr */
 	u32	cfg_data;	/* PCIX Configuration Data */
 	u32	int_ack;	/* PCIX IRQ Acknowledge */
-	u8	res1[3060];
+	u8	res000c[52];
+	u32	liodn_base;	/* PCIX LIODN base register */
+	u8	res0044[3004];
 	u32	potar0;		/* PCIX Outbound Transaction Addr 0 */
 	u32	potear0;	/* PCIX Outbound Translation Extended Addr 0 */
 	u32	powbar0;	/* PCIX Outbound Window Base Addr 0 */
@@ -1687,6 +1689,77 @@ typedef struct ccsr_gur {
 	u32	alt_pmuxcr;	/* Alt function signal multiplex control */
 	u8	res6[12];
 	u32	devdisr;	/* Device disable control */
+	u32	devdisr2;	/* Device disable control 2 */
+	u32	devdisr3;	/* Device disable control 3 */
+	u32	devdisr4;	/* Device disable control 4 */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	u32	devdisr5;	/* Device disable control 5 */
+#define FSL_CORENET_DEVDISR_PBL	0x80000000
+#define FSL_CORENET_DEVDISR_PMAN	0x40000000
+#define FSL_CORENET_DEVDISR_ESDHC	0x20000000
+#define FSL_CORENET_DEVDISR_DMA1	0x00800000
+#define FSL_CORENET_DEVDISR_DMA2	0x00400000
+#define FSL_CORENET_DEVDISR_USB1	0x00080000
+#define FSL_CORENET_DEVDISR_USB2	0x00040000
+#define FSL_CORENET_DEVDISR_SATA1	0x00008000
+#define FSL_CORENET_DEVDISR_SATA2	0x00004000
+#define FSL_CORENET_DEVDISR_PME	0x00000800
+#define FSL_CORENET_DEVDISR_SEC	0x00000200
+#define FSL_CORENET_DEVDISR_RMU	0x00000080
+#define FSL_CORENET_DEVDISR_DCE	0x00000040
+#define FSL_CORENET_DEVDISR2_DTSEC1_1	0x80000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2	0x40000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3	0x20000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4	0x10000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5	0x08000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_6	0x04000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_9	0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_10	0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_1	0x00800000
+#define FSL_CORENET_DEVDISR2_10GEC1_2	0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00080000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00040000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00020000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_6	0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_9	0x00000800
+#define FSL_CORENET_DEVDISR2_DTSEC2_10	0x00000400
+#define FSL_CORENET_DEVDISR2_10GEC2_1	0x00000800
+#define FSL_CORENET_DEVDISR2_10GEC2_2	0x00000400
+#define FSL_CORENET_DEVDISR2_FM1	0x00000080
+#define FSL_CORENET_DEVDISR2_FM2	0x00000040
+#define FSL_CORENET_DEVDISR2_CPRI	0x00000008
+#define FSL_CORENET_DEVDISR3_PCIE1	0x80000000
+#define FSL_CORENET_DEVDISR3_PCIE2	0x40000000
+#define FSL_CORENET_DEVDISR3_PCIE3	0x20000000
+#define FSL_CORENET_DEVDISR3_PCIE4	0x10000000
+#define FSL_CORENET_DEVDISR3_SRIO1	0x08000000
+#define FSL_CORENET_DEVDISR3_SRIO2	0x04000000
+#define FSL_CORENET_DEVDISR3_QMAN	0x00080000
+#define FSL_CORENET_DEVDISR3_BMAN	0x00040000
+#define FSL_CORENET_DEVDISR3_LA1	0x00008000
+#define FSL_CORENET_DEVDISR3_MAPLE1	0x00000800
+#define FSL_CORENET_DEVDISR3_MAPLE2	0x00000400
+#define FSL_CORENET_DEVDISR3_MAPLE3	0x00000200
+#define FSL_CORENET_DEVDISR4_I2C1	0x80000000
+#define FSL_CORENET_DEVDISR4_I2C2	0x40000000
+#define FSL_CORENET_DEVDISR4_DUART1	0x20000000
+#define FSL_CORENET_DEVDISR4_DUART2	0x10000000
+#define FSL_CORENET_DEVDISR4_ESPI	0x08000000
+#define FSL_CORENET_DEVDISR5_DDR1	0x80000000
+#define FSL_CORENET_DEVDISR5_DDR2	0x40000000
+#define FSL_CORENET_DEVDISR5_DDR3	0x20000000
+#define FSL_CORENET_DEVDISR5_CPC1	0x08000000
+#define FSL_CORENET_DEVDISR5_CPC2	0x04000000
+#define FSL_CORENET_DEVDISR5_CPC3	0x02000000
+#define FSL_CORENET_DEVDISR5_IFC	0x00800000
+#define FSL_CORENET_DEVDISR5_GPIO	0x00400000
+#define FSL_CORENET_DEVDISR5_DBG	0x00200000
+#define FSL_CORENET_DEVDISR5_NAL	0x00100000
+#define FSL_CORENET_DEVDISR5_TIMERS	0x00020000
+#define FSL_CORENET_NUM_DEVDISR		5
+#else
 #define FSL_CORENET_DEVDISR_PCIE1	0x80000000
 #define FSL_CORENET_DEVDISR_PCIE2	0x40000000
 #define FSL_CORENET_DEVDISR_PCIE3	0x20000000
@@ -1712,7 +1785,6 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR_I2C2	0x00000010
 #define FSL_CORENET_DEVDISR_DUART1	0x00000002
 #define FSL_CORENET_DEVDISR_DUART2	0x00000001
-	u32	devdisr2;	/* Device disable control 2 */
 #define FSL_CORENET_DEVDISR2_PME	0x80000000
 #define FSL_CORENET_DEVDISR2_SEC	0x40000000
 #define FSL_CORENET_DEVDISR2_QMBM	0x08000000
@@ -1731,8 +1803,8 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00001000
 #define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00000800
 #define FSL_CORENET_NUM_DEVDISR		2
-	u8	res7[8];
 	u32	powmgtcsr;	/* Power management status & control */
+#endif
 	u8	res8[12];
 	u32	coredisru;	/* uppper portion for support of 64 cores */
 	u32	coredisrl;	/* lower portion for support of 64 cores */
@@ -1755,13 +1827,47 @@ typedef struct ccsr_gur {
 	u32	brrl;		/* Boot release */
 	u8	res17[24];
 	u32	rcwsr[16];	/* Reset control word status */
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	16
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#if defined(CONFIG_PPC_T4240)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xfc000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	26
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL		0x0000f800
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT	11
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL		0x000000f8
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT	3
+#elif defined(CONFIG_PPC_B4860)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xfe000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
+#endif
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1	0x00200000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2	0x00100000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1	0x00080000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2	0x00040000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1	0x00020000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2	0x00010000
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x1f
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
 #define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
 #define FSL_CORENET_RCWSR5_SRDS_EN		0x00002000
+#define FSL_CORENET_RCWSR5_SRDS2_EN		0x00001000
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2		0x3c000000 /* bits 162..165 */
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3		0x003c0000 /* bits 170..173 */
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000
@@ -1784,6 +1890,24 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII		0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE		0x00180000
 #endif
+#if defined(CONFIG_PPC_P5040)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII        0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII          0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE         0x00c00000
+#define FSL_CORENET_RCWSR11_EC2                 0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII        0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
+#endif
+#if defined(CONFIG_PPC_T4240)
+#define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO		0x40000000
+#define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII	0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
+#endif
 	u8	res18[192];
 	u32	scratchrw[4];	/* Scratch Read/Write */
 	u8	res19[240];
@@ -1880,34 +2004,38 @@ typedef struct ccsr_gur {
 #define rmuliodnr rio1maintliodnr
 
 typedef struct ccsr_clk {
-	u32	clkc0csr;	/* Core 0 Clock control/status */
+	u32	clkc0csr;	/* 0x000 Core 0 Clock control/status */
 	u8	res1[0x1c];
-	u32	clkc1csr;	/* Core 1 Clock control/status */
+	u32	clkc1csr;	/* 0x020 Core 1 Clock control/status */
 	u8	res2[0x1c];
-	u32	clkc2csr;	/* Core 2 Clock control/status */
+	u32	clkc2csr;	/* 0x040 Core 2 Clock control/status */
 	u8	res3[0x1c];
-	u32	clkc3csr;	/* Core 3 Clock control/status */
+	u32	clkc3csr;	/* 0x060 Core 3 Clock control/status */
 	u8	res4[0x1c];
-	u32	clkc4csr;	/* Core 4 Clock control/status */
+	u32	clkc4csr;	/* 0x080 Core 4 Clock control/status */
 	u8	res5[0x1c];
-	u32	clkc5csr;	/* Core 5 Clock control/status */
+	u32	clkc5csr;	/* 0x0a0 Core 5 Clock control/status */
 	u8	res6[0x1c];
-	u32	clkc6csr;	/* Core 6 Clock control/status */
+	u32	clkc6csr;	/* 0x0c0 Core 6 Clock control/status */
 	u8	res7[0x1c];
-	u32	clkc7csr;	/* Core 7 Clock control/status */
+	u32	clkc7csr;	/* 0x0e0 Core 7 Clock control/status */
 	u8	res8[0x71c];
-	u32	pllc1gsr;	/* Cluster PLL 1 General Status */
+	u32	pllc1gsr;	/* 0x800 Cluster PLL 1 General Status */
 	u8	res10[0x1c];
-	u32	pllc2gsr;	/* Cluster PLL 2 General Status */
+	u32	pllc2gsr;	/* 0x820 Cluster PLL 2 General Status */
 	u8	res11[0x1c];
-	u32	pllc3gsr;	/* Cluster PLL 3 General Status */
+	u32	pllc3gsr;	/* 0x840 Cluster PLL 3 General Status */
 	u8	res12[0x1c];
-	u32	pllc4gsr;	/* Cluster PLL 4 General Status */
-	u8	res13[0x39c];
-	u32	pllpgsr;	/* Platform PLL General Status */
+	u32	pllc4gsr;	/* 0x860 Cluster PLL 4 General Status */
+	u8	res13[0x1c];
+	u32	pllc5gsr;	/* 0x880 Cluster PLL 5 General Status */
 	u8	res14[0x1c];
-	u32	plldgsr;	/* DDR PLL General Status */
-	u8	res15[0x3dc];
+	u32	pllc6gsr;	/* 0x8a0 Cluster PLL 6 General Status */
+	u8	res15[0x35c];
+	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
+	u8	res16[0x1c];
+	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
+	u8	res17[0x3dc];
 } ccsr_clk_t;
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
@@ -2384,6 +2512,78 @@ typedef struct ccsr_gur {
 
 #define SDHCDCR_CD_INV		0x80000000 /* invert SDHC card detect */
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define MAX_SERDES 4
+#define SRDS_MAX_LANES 8
+#define SRDS_MAX_BANK 2
+typedef struct serdes_corenet {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+#define SRDS_RSTCTL_RST		0x80000000
+#define SRDS_RSTCTL_RSTDONE	0x40000000
+#define SRDS_RSTCTL_RSTERR	0x20000000
+#define SRDS_RSTCTL_SWRST	0x10000000
+#define SRDS_RSTCTL_SDPD	0x00000020
+		u32	pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF		0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+		u32	pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
+		u32	res_0c;	/* 0x00c */
+		u32	pllcr3;
+		u32	pllcr4;
+		u8	res_18[0x20-0x18];
+	} bank[2];
+	u8	res_40[0x90-0x40];
+	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
+	u8	res_94[0xa0-0x94];
+	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
+	u8	res_a4[0xb0-0xa4];
+	u32	srdsgr0;	/* 0xb0 General Register 0 */
+	u8	res_b4[0xe0-0xb4];
+	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
+	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
+	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
+	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
+	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
+	u8	res_f4[0x100-0xf4];
+	struct {
+		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
+		u8	res_104[0x120-0x104];
+	} srdslnpssr[8];
+	u8	res_200[0x800-0x200];
+	struct {
+		u32	gcr0;	/* 0x800 General Control Register 0 */
+		u32	gcr1;	/* 0x804 General Control Register 1 */
+		u32	gcr2;	/* 0x808 General Control Register 2 */
+		u32	res_80c;
+		u32	recr0;	/* 0x810 Receive Equalization Control */
+		u32	res_814;
+		u32	tecr0;	/* 0x818 Transmit Equalization Control */
+		u32	res_81c;
+		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
+		u8	res_824[0x840-0x824];
+	} lane[8];	/* Lane A, B, C, D, E, F, G, H */
+	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
+} serdes_corenet_t;
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define SRDS_MAX_LANES		18
+#define SRDS_MAX_BANK		3
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */
@@ -2392,11 +2592,13 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_RSTERR	0x20000000
 #define SRDS_RSTCTL_SDPD	0x00000020
 		u32	pllcr0; /* PLL Control Register 0 */
-#define SRDS_PLLCR0_RFCK_SEL_MASK	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_PVCOCNT_EN		0x02000000
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_6_25	0x00010000
@@ -2421,6 +2623,7 @@ typedef struct serdes_corenet {
 		u32	gcr0;	/* General Control Register 0 */
 #define SRDS_GCR0_RRST			0x00400000
 #define SRDS_GCR0_1STLANE		0x00010000
+#define SRDS_GCR0_UOTHL			0x00100000
 		u32	gcr1;	/* General Control Register 1 */
 #define SRDS_GCR1_REIDL_CTL_MASK	0x001f0000
 #define SRDS_GCR1_REIDL_CTL_PCIE	0x00100000
@@ -2440,6 +2643,7 @@ typedef struct serdes_corenet {
 	} lane[24];
 	u32 res6[384];
 } serdes_corenet_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 enum {
 	FSL_SRDS_B1_LANE_A = 0,
@@ -2482,8 +2686,8 @@ typedef struct ccsr_sec {
 	struct {
 		u32	ms;	/* DECO LIODN Register, MS */
 		u32	ls;	/* DECO LIODN Register, LS */
-	} decoliodnr[5];
-	u8	res4[0x58];
+	} decoliodnr[8];
+	u8	res4[0x40];
 	u32	dar;		/* DECO Avail Register */
 	u32	drr;		/* DECO Reset Register */
 	u8	res5[0xe78];
@@ -2523,13 +2727,16 @@ typedef struct ccsr_sec {
 #endif
 
 typedef struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	u8	res0[0x200];
+#else
 	struct {
 		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
 		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
 		u32	res;
 		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg */
 	} qcsp[32];
-
+#endif
 	/* Not actually reserved, but irrelevant to u-boot */
 	u8	res[0xbf8 - 0x200];
 	u32	ip_rev_1;
@@ -2554,6 +2761,14 @@ typedef struct ccsr_qman {
 	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
 	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
 	u8	res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
+	} qcsp[50];
+#endif
 } ccsr_qman_t;
 
 typedef struct ccsr_bman {
@@ -2617,14 +2832,48 @@ struct ccsr_rman {
 };
 #endif
 
+#ifdef CONFIG_SYS_PMAN
+struct ccsr_pman {
+	u8	res_00[0x40];
+	u32	poes1;		/* PMAN Operation Error Status Register 1 */
+	u32	poes2;		/* PMAN Operation Error Status Register 2 */
+	u32	poeah;		/* PMAN Operation Error Address High */
+	u32	poeal;		/* PMAN Operation Error Address Low */
+	u8	res_50[0x50];
+	u32	pr1;		/* PMAN Revision Register 1 */
+	u32	pr2;		/* PMAN Revision Register 2 */
+	u8	res_a8[0x8];
+	u32	pcap;		/* PMAN Capabilities Register */
+	u8	res_b4[0xc];
+	u32	pc1;		/* PMAN Control Register 1 */
+	u32	pc2;		/* PMAN Control Register 2 */
+	u32	pc3;		/* PMAN Control Register 3 */
+	u32	pc4;		/* PMAN Control Register 4 */
+	u32	pc5;		/* PMAN Control Register 5 */
+	u32	pc6;		/* PMAN Control Register 6 */
+	u8	res_d8[0x8];
+	u32	ppa1;		/* PMAN Prefetch Attributes Register 1 */
+	u32	ppa2;		/* PMAN Prefetch Attributes Register 2 */
+	u8	res_e8[0x8];
+	u32	pics;		/* PMAN Interrupt Control and Status */
+	u8	res_f4[0xf0c];
+};
+#endif
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
+#ifdef CONFIG_SYS_PMAN
+#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET	0x4000
+#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET	0x5000
+#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET	0x6000
+#endif
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x8000
 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET		0x9000
 #define CONFIG_SYS_MPC85xx_DDR3_OFFSET		0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
+#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
@@ -2635,10 +2884,17 @@ struct ccsr_rman {
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
+#else
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
+#endif
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET		CONFIG_SYS_MPC85xx_USB1_OFFSET
@@ -2657,7 +2913,9 @@ struct ccsr_rman {
 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0x48a000
 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0x48b000
 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0x48c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0x48d000
 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET	0x490000
+#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET	0x491000
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x4e0000
 #define CONFIG_SYS_FSL_FM2_OFFSET		0x500000
 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET	0x588000
@@ -2665,7 +2923,10 @@ struct ccsr_rman {
 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET	0x58a000
 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET	0x58b000
 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET	0x58c000
+#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET	0x58d000
 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET	0x590000
+#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
+#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
 #else
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x2000
@@ -2775,6 +3036,8 @@ struct ccsr_rman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
@@ -2808,4 +3071,62 @@ struct ccsr_rman {
 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+struct ccsr_cluster_l2 {
+	u32 l2csr0;	/* 0x000 L2 cache control and status register 0 */
+	u32 l2csr1;	/* 0x004 L2 cache control and status register 1 */
+	u32 l2cfg0;	/* 0x008 L2 cache configuration register 0 */
+	u8  res_0c[500];/* 0x00c - 0x1ff */
+	u32 l2pir0;	/* 0x200 L2 cache partitioning ID register 0 */
+	u8  res_204[4];
+	u32 l2par0;	/* 0x208 L2 cache partitioning allocation register 0 */
+	u32 l2pwr0;	/* 0x20c L2 cache partitioning way register 0 */
+	u32 l2pir1;	/* 0x210 L2 cache partitioning ID register 1 */
+	u8  res_214[4];
+	u32 l2par1;	/* 0x218 L2 cache partitioning allocation register 1 */
+	u32 l2pwr1;	/* 0x21c L2 cache partitioning way register 1 */
+	u32 u2pir2;	/* 0x220 L2 cache partitioning ID register 2 */
+	u8  res_224[4];
+	u32 l2par2;	/* 0x228 L2 cache partitioning allocation register 2 */
+	u32 l2pwr2;	/* 0x22c L2 cache partitioning way register 2 */
+	u32 l2pir3;	/* 0x230 L2 cache partitioning ID register 3 */
+	u8  res_234[4];
+	u32 l2par3;	/* 0x238 L2 cache partitining allocation register 3 */
+	u32 l2pwr3;	/* 0x23c L2 cache partitining way register 3 */
+	u32 l2pir4;	/* 0x240 L2 cache partitioning ID register 3 */
+	u8  res244[4];
+	u32 l2par4;	/* 0x248 L2 cache partitioning allocation register 3 */
+	u32 l2pwr4;	/* 0x24c L2 cache partitioning way register 3 */
+	u32 l2pir5;	/* 0x250 L2 cache partitioning ID register 3 */
+	u8  res_254[4];
+	u32 l2par5;	/* 0x258 L2 cache partitioning allocation register 3 */
+	u32 l2pwr5;	/* 0x25c L2 cache partitioning way register 3 */
+	u32 l2pir6;	/* 0x260 L2 cache partitioning ID register 3 */
+	u8  res_264[4];
+	u32 l2par6;	/* 0x268 L2 cache partitioning allocation register 3 */
+	u32 l2pwr6;	/* 0x26c L2 cache partitioning way register 3 */
+	u32 l2pir7;	/* 0x270 L2 cache partitioning ID register 3 */
+	u8  res274[4];
+	u32 l2par7;	/* 0x278 L2 cache partitioning allocation register 3 */
+	u32 l2pwr7;	/* 0x27c L2 cache partitioning way register 3 */
+	u8  res_280[0xb80]; /* 0x280 - 0xdff */
+	u32 l2errinjhi;	/* 0xe00 L2 cache error injection mask high */
+	u32 l2errinjlo;	/* 0xe04 L2 cache error injection mask low */
+	u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
+	u8  res_e0c[20];	/* 0xe0c - 0x01f */
+	u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
+	u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
+	u32 l2captecc;	/* 0xe28 L2 cache error capture ECC syndrome */
+	u8  res_e2c[20];	/* 0xe2c - 0xe3f */
+	u32 l2errdet;	/* 0xe40 L2 cache error detect */
+	u32 l2errdis;	/* 0xe44 L2 cache error disable */
+	u32 l2errinten;	/* 0xe48 L2 cache error interrupt enable */
+	u32 l2errattr;	/* 0xe4c L2 cache error attribute */
+	u32 l2erreaddr;	/* 0xe50 L2 cache error extended address */
+	u32 l2erraddr;	/* 0xe54 L2 cache error address */
+	u32 l2errctl;	/* 0xe58 L2 cache error control */
+};
+#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #endif /*__IMMAP_85xx__*/
diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h
index fe490ba..9188ede 100644
--- a/arch/powerpc/include/asm/mp.h
+++ b/arch/powerpc/include/asm/mp.h
@@ -25,7 +25,7 @@
 
 void setup_mp(void);
 void cpu_mp_lmb_reserve(struct lmb *lmb);
-u32 determine_mp_bootpg(void);
+u32 determine_mp_bootpg(unsigned int *pagesize);
 int is_core_disabled(int nr);
 
 #ifdef CONFIG_E6500
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 5a608a5..2aed514 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -98,7 +98,10 @@ static inline int gpio_direction_input(unsigned gpio)
 
 static inline int gpio_direction_output(unsigned gpio, int value)
 {
-	mpc85xx_gpio_set_low(1U << gpio);
+	if (value)
+		mpc85xx_gpio_set_high(1U << gpio);
+	else
+		mpc85xx_gpio_set_low(1U << gpio);
 	return 0;
 }
 
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 36695e2..7aa3231 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1095,6 +1095,17 @@
 #define SVR_P4080	0x820000
 #define SVR_P5010	0x822100
 #define SVR_P5020	0x822000
+#define SVR_P5021	0X820500
+#define SVR_P5040	0x820400
+#define SVR_T4240	0x824000
+#define SVR_T4120	0x824001
+#define SVR_B4860	0X868000
+#define SVR_G4860	0x868001
+#define SVR_G4060	0x868003
+#define SVR_B4440	0x868100
+#define SVR_G4440	0x868101
+#define SVR_B4420	0x868102
+#define SVR_B4220	0x868103
 
 #define SVR_8610	0x80A000
 #define SVR_8641	0x809000
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index b860141..ebf4008 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -440,8 +440,8 @@ void board_init_f(ulong bootflag)
 	 * We need to make sure the location we intend to put secondary core
 	 * boot code is reserved and not used by any part of u-boot
 	 */
-	if (addr > determine_mp_bootpg()) {
-		addr = determine_mp_bootpg();
+	if (addr > determine_mp_bootpg(NULL)) {
+		addr = determine_mp_bootpg(NULL);
 		debug("Reserving MP boot page to %08lx\n", addr);
 	}
 #endif