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| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2011-02-07 15:09:51 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-04 09:24:41 -0500 |
| commit | 0b3b1766b78331dfd109f2c5f816dcdd65055eb6 (patch) | |
| tree | 9751e6cd8a6c51d75376ce8326758ef39b3f4131 /arch/powerpc | |
| parent | 09f9ee1695136045f293dacda915d94c2891d4f0 (diff) | |
| download | u-boot-imx-0b3b1766b78331dfd109f2c5f816dcdd65055eb6.zip u-boot-imx-0b3b1766b78331dfd109f2c5f816dcdd65055eb6.tar.gz u-boot-imx-0b3b1766b78331dfd109f2c5f816dcdd65055eb6.tar.bz2 | |
fsl_ddr: Adds 16 bit DDR Data width option
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/util.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 1 |
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index 815c5e3..b9a5a69 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -139,6 +139,8 @@ void board_add_ram_info(int use_default) if (sdram_cfg & SDRAM_CFG_32_BE) puts(", 32-bit"); + else if (sdram_cfg & SDRAM_CFG_16_BE) + puts(", 16-bit"); else puts(", 64-bit"); diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index b5b1efe..99dddb4 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -84,6 +84,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 #define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_2T_EN 0x00008000 |