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| author | Valentin Longchamp <valentin.longchamp@keymile.com> | 2015-03-27 16:07:32 +0100 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-05-04 09:24:42 -0700 |
| commit | ac337168ad81a18e768e5e3cfff8d229adeb2b25 (patch) | |
| tree | 0170438bc190b71d7dc82c6f8f8863923e67d77d /arch/powerpc/lib | |
| parent | e8a7f1c32b55f48408a10cded2663b3f578d02e2 (diff) | |
| download | u-boot-imx-ac337168ad81a18e768e5e3cfff8d229adeb2b25.zip u-boot-imx-ac337168ad81a18e768e5e3cfff8d229adeb2b25.tar.gz u-boot-imx-ac337168ad81a18e768e5e3cfff8d229adeb2b25.tar.bz2 | |
powerpc: add 2 common dcache assembly functions
This patch defines the 2 flush_dcache_range and invalidate_dcache_range
functions for all the powerpc architecture. Their implementation is
borrowed from the kernel's misc_32.S file and replace the ones from
mpc86xx and ppc4xx since they were equivalent.
This is a fix for the problem introduced by this patch:
http://patchwork.ozlabs.org/patch/448849/
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/lib')
| -rw-r--r-- | arch/powerpc/lib/ppccache.S | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index 349a1c1..b96dbc6 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -9,6 +9,9 @@ #include <config.h> #include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> /*------------------------------------------------------------------------------- */ /* Function: ppcDcbf */ @@ -54,3 +57,48 @@ ppcDcbz: ppcSync: sync blr + +/* + * Write any modified data cache blocks out to memory and invalidate them. + * Does not invalidate the corresponding instruction cache blocks. + * + * flush_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + +1: dcbf 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Like above, but invalidate the D-cache. This is used by the 8xx + * to invalidate the cache so the PPC core doesn't get stale data + * from the CPM (no cache snooping here :-). + * + * invalidate_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(invalidate_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + + sync +1: dcbi 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbi's to get to ram */ + blr + |