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authorZang Roy-R61911 <tie-fei.zang@freescale.com>2013-11-28 13:23:37 +0800
committerYork Sun <yorksun@freescale.com>2013-12-04 14:54:42 -0800
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T4240: Address T4240/T4160 Rev2.0 DDR clock change
MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0. It's 12 in Rev1.0, for Rev2.0 it uses 6. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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