diff options
author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:19 +0000 |
---|---|---|
committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:23 -0500 |
commit | 9e758758491b0d7a71bdf1db8cd860b599d7e657 (patch) | |
tree | fc88acc8d8635606a0236aab768417741c4bb18c /arch/powerpc/include | |
parent | f311838ded0c4b08726e5a363d518babc2109493 (diff) | |
download | u-boot-imx-9e758758491b0d7a71bdf1db8cd860b599d7e657.zip u-boot-imx-9e758758491b0d7a71bdf1db8cd860b599d7e657.tar.gz u-boot-imx-9e758758491b0d7a71bdf1db8cd860b599d7e657.tar.bz2 |
powerpc/mpc85xx: Add T4240 SoC
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 28 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 87 | ||||
-rw-r--r-- | arch/powerpc/include/asm/processor.h | 2 |
3 files changed, 115 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index a61d315..cfa5448 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -482,6 +482,34 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#elif defined(CONFIG_PPC_T4240) +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_MAX_CPUS 12 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SRDS_3 +#define CONFIG_SYS_FSL_SRDS_4 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_SYS_NUM_FM2_DTSEC 8 +#define CONFIG_SYS_NUM_FM2_10GEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 51f02fc..5001f6e 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1689,6 +1689,72 @@ typedef struct ccsr_gur { u32 alt_pmuxcr; /* Alt function signal multiplex control */ u8 res6[12]; u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + u32 devdisr5; /* Device disable control 5 */ +#define FSL_CORENET_DEVDISR_PBL 0x80000000 +#define FSL_CORENET_DEVDISR_PMAN 0x40000000 +#define FSL_CORENET_DEVDISR_ESDHC 0x20000000 +#define FSL_CORENET_DEVDISR_DMA1 0x00800000 +#define FSL_CORENET_DEVDISR_DMA2 0x00400000 +#define FSL_CORENET_DEVDISR_USB1 0x00080000 +#define FSL_CORENET_DEVDISR_USB2 0x00040000 +#define FSL_CORENET_DEVDISR_SATA1 0x00008000 +#define FSL_CORENET_DEVDISR_SATA2 0x00004000 +#define FSL_CORENET_DEVDISR_PME 0x00000800 +#define FSL_CORENET_DEVDISR_SEC 0x00000200 +#define FSL_CORENET_DEVDISR_RMU 0x00000080 +#define FSL_CORENET_DEVDISR_DCE 0x00000040 +#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 +#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 +#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 +#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 +#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 +#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 +#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 +#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000 +#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000 +#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000 +#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800 +#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400 +#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800 +#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400 +#define FSL_CORENET_DEVDISR2_FM1 0x00000080 +#define FSL_CORENET_DEVDISR2_FM2 0x00000040 +#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000 +#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000 +#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000 +#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000 +#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000 +#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000 +#define FSL_CORENET_DEVDISR3_QMAN 0x00080000 +#define FSL_CORENET_DEVDISR3_BMAN 0x00040000 +#define FSL_CORENET_DEVDISR3_LA1 0x00008000 +#define FSL_CORENET_DEVDISR4_I2C1 0x80000000 +#define FSL_CORENET_DEVDISR4_I2C2 0x40000000 +#define FSL_CORENET_DEVDISR4_DUART1 0x20000000 +#define FSL_CORENET_DEVDISR4_DUART2 0x10000000 +#define FSL_CORENET_DEVDISR4_ESPI 0x08000000 +#define FSL_CORENET_DEVDISR5_DDR1 0x80000000 +#define FSL_CORENET_DEVDISR5_DDR2 0x40000000 +#define FSL_CORENET_DEVDISR5_DDR3 0x20000000 +#define FSL_CORENET_DEVDISR5_CPC1 0x08000000 +#define FSL_CORENET_DEVDISR5_CPC2 0x04000000 +#define FSL_CORENET_DEVDISR5_CPC3 0x02000000 +#define FSL_CORENET_DEVDISR5_IFC 0x00800000 +#define FSL_CORENET_DEVDISR5_GPIO 0x00400000 +#define FSL_CORENET_DEVDISR5_DBG 0x00200000 +#define FSL_CORENET_DEVDISR5_NAL 0x00100000 +#define FSL_CORENET_NUM_DEVDISR 5 +#else #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 @@ -1714,7 +1780,6 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR_I2C2 0x00000010 #define FSL_CORENET_DEVDISR_DUART1 0x00000002 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 - u32 devdisr2; /* Device disable control 2 */ #define FSL_CORENET_DEVDISR2_PME 0x80000000 #define FSL_CORENET_DEVDISR2_SEC 0x40000000 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000 @@ -1733,8 +1798,8 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800 #define FSL_CORENET_NUM_DEVDISR 2 - u8 res7[8]; u32 powmgtcsr; /* Power management status & control */ +#endif u8 res8[12]; u32 coredisru; /* uppper portion for support of 64 cores */ u32 coredisrl; /* lower portion for support of 64 cores */ @@ -1761,6 +1826,7 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#if defined(CONFIG_PPC_T4240) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1769,6 +1835,7 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 +#endif #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000 @@ -1822,6 +1889,15 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif +#if defined(CONFIG_PPC_T4240) +#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ +#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 +#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 +#endif u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res19[240]; @@ -2798,10 +2874,17 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 +#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 +#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000 +#else #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 +#endif #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fd0160a..5bc0da6 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1097,6 +1097,8 @@ #define SVR_P5020 0x822000 #define SVR_P5021 0X820500 #define SVR_P5040 0x820400 +#define SVR_T4240 0x824000 +#define SVR_T4120 0x824001 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 |