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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:24 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:27 -0500 |
| commit | f31cfd19253713eea59311dec9e99df5d43b2db9 (patch) | |
| tree | 61e6f45481b4efa6949c5456fe81dcf0135480e6 /arch/powerpc/include | |
| parent | 123922b1e583dc6bd6b8909af2d788f6e40a33a9 (diff) | |
| download | u-boot-imx-f31cfd19253713eea59311dec9e99df5d43b2db9.zip u-boot-imx-f31cfd19253713eea59311dec9e99df5d43b2db9.tar.gz u-boot-imx-f31cfd19253713eea59311dec9e99df5d43b2db9.tar.bz2 | |
powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT
When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index bb79335..640d329 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -98,6 +98,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_DBW_MASK 0x00180000 +#define SDRAM_CFG_DBW_SHIFT 19 #define SDRAM_CFG_32_BE 0x00080000 #define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 @@ -330,6 +331,7 @@ extern phys_size_t fsl_ddr_sdram_size(void); extern int fsl_use_spd(void); extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); +u32 fsl_ddr_get_intl3r(void); /* * The 85xx boards have a common prototype for fixed_sdram so put the |