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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:23 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:26 -0500 |
| commit | 123922b1e583dc6bd6b8909af2d788f6e40a33a9 (patch) | |
| tree | ed286734f765f1b12624b4ea9b878b6e94173569 /arch/powerpc/include | |
| parent | 57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2 (diff) | |
| download | u-boot-imx-123922b1e583dc6bd6b8909af2d788f6e40a33a9.zip u-boot-imx-123922b1e583dc6bd6b8909af2d788f6e40a33a9.tar.gz u-boot-imx-123922b1e583dc6bd6b8909af2d788f6e40a33a9.tar.bz2 | |
powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation
Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.
For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.
Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.
Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.
It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 9cf9bd4..bb79335 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -84,6 +84,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D +#define SDRAM_CS_CONFIG_EN 0x80000000 + /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ #define SDRAM_CFG_MEM_EN 0x80000000 |