diff options
| author | York Sun <york.sun@nxp.com> | 2016-11-21 13:31:34 -0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-11-23 23:42:15 -0800 |
| commit | 652a7bbd87d322c49ffe138b98563dc6c8cd2885 (patch) | |
| tree | b228c46847036e5d745ae04dae1ef93ffb6303fa /arch/powerpc/include | |
| parent | 49ec8aa8403061c654cc3afa57cf8cd570b0a8a0 (diff) | |
| download | u-boot-imx-652a7bbd87d322c49ffe138b98563dc6c8cd2885.zip u-boot-imx-652a7bbd87d322c49ffe138b98563dc6c8cd2885.tar.gz u-boot-imx-652a7bbd87d322c49ffe138b98563dc6c8cd2885.tar.bz2 | |
powerpc: T4160: Remove macro CONFIG_PPC_T4160
Use CONFIG_ARCH_T4160 instead.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 65a4777..fc8e011 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -545,7 +545,7 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -568,7 +568,7 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 -#if defined(CONFIG_PPC_T4160) +#if defined(CONFIG_ARCH_T4160) #define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #elif defined(CONFIG_PPC_T4080) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 783db18..19ce7f3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,7 +1759,7 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 @@ -1875,7 +1875,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 |