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authorYork Sun <yorksun@freescale.com>2011-08-26 11:32:40 -0700
committerKumar Gala <galak@kernel.crashing.org>2011-09-29 19:01:06 -0500
commitcae7c1b56b4f59289a1b2f10532c2c6a0b12c6c1 (patch)
tree9cf014b86bf2a604c48a8307d64a6ccc34b83516 /arch/powerpc/include
parentf8bc7bb5a79b392db3af9f62b63caefab8afbc31 (diff)
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powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_sdram.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index bc063ea..5b6e8d9 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -92,6 +92,10 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define SDRAM_CFG2_D_INIT 0x00000010
#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
+#define SDRAM_CFG2_ODT_NEVER 0
+#define SDRAM_CFG2_ODT_ONLY_WRITE 1
+#define SDRAM_CFG2_ODT_ONLY_READ 2
+#define SDRAM_CFG2_ODT_ALWAYS 3
#define TIMING_CFG_2_CPO_MASK 0x0F800000