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authorKumar Gala <galak@kernel.crashing.org>2011-11-22 06:51:15 -0600
committerKumar Gala <galak@kernel.crashing.org>2011-11-29 08:48:05 -0600
commit43f082bb7fc1c24b32a4abc693869c7d14d42829 (patch)
tree93f965962cb64edbac52e2ff28125641a68a9299 /arch/powerpc/include
parenta63d9652757605ec5f7104addc5d38bf10ba8671 (diff)
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powerpc/85xx: Add workaround for erratum CPU-A003999
Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 981d639..f1da82e 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -313,6 +313,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P2041)
#define CONFIG_MAX_CPUS 4
@@ -331,6 +332,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4
@@ -349,6 +351,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P3060)
#define CONFIG_MAX_CPUS 8
@@ -364,6 +367,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P4040)
#define CONFIG_MAX_CPUS 4
@@ -374,6 +378,7 @@
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
@@ -402,6 +407,7 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
+#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
/* P5010 is single core version of P5020 */
#elif defined(CONFIG_PPC_P5010)