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authorPrabhakar Kushwaha <prabhakar@freescale.com>2013-09-03 11:20:15 +0530
committerYork Sun <yorksun@freescale.com>2013-10-16 16:13:11 -0700
commitce746fe03eb42b97a1510fe0243662f0ae56eecd (patch)
tree7dcd6e83eba11aa2e450f640f66deea2ee21213b /arch/powerpc/include
parent1d384eca61b4bb799537515078cfc541d51bbc64 (diff)
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powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator
CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h14
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h21
2 files changed, 21 insertions, 14 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index ba6b6ff..b51d383 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -558,6 +558,7 @@
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#ifdef CONFIG_PPC_T4240
#define CONFIG_MAX_CPUS 12
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
@@ -565,6 +566,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 3
#else
#define CONFIG_MAX_CPUS 8
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 7
@@ -579,9 +581,12 @@
#define CONFIG_SYS_FSL_SRDS_4
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM1_CLK 3
+#define CONFIG_SYS_FM2_CLK 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
@@ -609,6 +614,7 @@
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
@@ -625,6 +631,7 @@
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 2
@@ -636,6 +643,7 @@
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#define CONFIG_NUM_DDR_CONTROLLERS 1
@@ -653,15 +661,21 @@
#define CONFIG_MAX_CPUS 2
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CONFIG_SYS_SDHC_CLOCK 0
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_PME_PLAT_CLK_DIV 2
+#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
+#define CONFIG_FM_PLAT_CLK_DIV 1
+#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 3a10d77..00f17b6 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2016,20 +2016,13 @@ typedef struct ccsr_clk {
u8 res_004[0x0c];
u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
u8 res_014[0x0c];
- } clkcsr[8];
- u8 res_100[0x700]; /* 0x100 */
- u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */
- u8 res10[0x1c];
- u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */
- u8 res11[0x1c];
- u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */
- u8 res12[0x1c];
- u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */
- u8 res13[0x1c];
- u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */
- u8 res14[0x1c];
- u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */
- u8 res15[0x35c];
+ } clkcsr[12];
+ u8 res_100[0x680]; /* 0x100 */
+ struct {
+ u32 pllcngsr;
+ u8 res10[0x1c];
+ } pllcgsr[12];
+ u8 res21[0x280];
u32 pllpgsr; /* 0xc00 Platform PLL General Status */
u8 res16[0x1c];
u32 plldgsr; /* 0xc20 DDR PLL General Status */