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author | Tom Rini <trini@ti.com> | 2013-08-14 15:16:48 -0400 |
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committer | Tom Rini <trini@ti.com> | 2013-08-14 15:16:48 -0400 |
commit | 120694bd714498cdd6245f0deb7091db7d1cdbf3 (patch) | |
tree | 0bdb89aa138cc98006525b00101cfef3b64d2b19 /arch/powerpc/include | |
parent | cdce889959c611876690a9f0a3c7ed9aa46189c4 (diff) | |
parent | 49d87b1325fde11ebac60d8dc1cbd4c2c11d3973 (diff) | |
download | u-boot-imx-120694bd714498cdd6245f0deb7091db7d1cdbf3.zip u-boot-imx-120694bd714498cdd6245f0deb7091db7d1cdbf3.tar.gz u-boot-imx-120694bd714498cdd6245f0deb7091db7d1cdbf3.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 4 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 48 |
2 files changed, 4 insertions, 48 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ce1bf05..e1fc0f7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -535,6 +535,8 @@ #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -565,6 +567,8 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 2ed384e..3a10d77 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2846,54 +2846,6 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t; -#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE -struct ccsr_usb_port_ctrl { - u32 ctrl; - u32 drvvbuscfg; - u32 pwrfltcfg; - u32 sts; - u8 res_14[0xc]; - u32 bistcfg; - u32 biststs; - u32 abistcfg; - u32 abiststs; - u8 res_30[0x10]; - u32 xcvrprg; - u32 anaprg; - u32 anadrv; - u32 anasts; -}; - -typedef struct ccsr_usb_phy { - u32 id; - struct ccsr_usb_port_ctrl port1; - u8 res_50[0xc]; - u32 tvr; - u32 pllprg[4]; - u8 res_70[0x4]; - u32 anaccfg; - u32 dbg; - u8 res_7c[0x4]; - struct ccsr_usb_port_ctrl port2; - u8 res_dc[0x334]; -} ccsr_usb_phy_t; - -#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) -#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) -#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) -#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) -#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) -#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) -#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) -#else -typedef struct ccsr_usb_phy { - u8 res0[0x18]; - u32 usb_enable_override; - u8 res[0xe4]; -} ccsr_usb_phy_t; -#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 -#endif - #ifdef CONFIG_SYS_FSL_RAID_ENGINE struct ccsr_raide { u8 res0[0x543]; |