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| author | Wolfgang Denk <wd@denx.de> | 2011-05-12 19:27:42 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-05-12 19:27:42 +0200 |
| commit | 0e0c0892a1fab6f93ba09d89ec3315f08f1b6ef4 (patch) | |
| tree | 2fe8aa31f12c433194a317d5edcee87fbef41cbc /arch/powerpc/include | |
| parent | 162eee41060896af666c70ae308d2bb13d971ccf (diff) | |
| parent | 644362c40aa8d356d2cc0d230ce0c3bad279c23c (diff) | |
| download | u-boot-imx-0e0c0892a1fab6f93ba09d89ec3315f08f1b6ef4.zip u-boot-imx-0e0c0892a1fab6f93ba09d89ec3315f08f1b6ef4.tar.gz u-boot-imx-0e0c0892a1fab6f93ba09d89ec3315f08f1b6ef4.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/ppc405ex.h | 5 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/processor.h | 31 |
2 files changed, 36 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h index 36d3149..8070385 100644 --- a/arch/powerpc/include/asm/ppc405ex.h +++ b/arch/powerpc/include/asm/ppc405ex.h @@ -43,6 +43,11 @@ #define SDR0_PFC1 0x4101 #define SDR0_MFR 0x4300 /* SDR0_MFR reg */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + #define SDR0_SDCS_SDD (0x80000000 >> 31) #define SDR0_SRST_DMC (0x80000000 >> 10) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index f5bf4dd..c5b03b4 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -974,6 +974,37 @@ #define PVR_5200B 0x80822014 /* + * 405EX/EXr CHIP_21 Errata + */ +#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY +#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC +#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD +#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0 +#endif + +#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY +#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC +#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD +#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1 +#endif + +#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY +#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC +#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD +#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2 +#endif + +#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY +#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC +#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD +#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3 +#endif + +/* * System Version Register */ |