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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2014-01-30 15:39:58 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-03-07 14:53:29 -0800 |
| commit | bf4699db852f88b0a30b9d7e8b1bea83d01c0d92 (patch) | |
| tree | 37f0fc6ca9fd11986e690cfe9f3bc4a1eb1441af /arch/powerpc/include | |
| parent | 8d67c3685e3b4bea8524e2e25b1443b62a69352b (diff) | |
| download | u-boot-imx-bf4699db852f88b0a30b9d7e8b1bea83d01c0d92.zip u-boot-imx-bf4699db852f88b0a30b9d7e8b1bea83d01c0d92.tar.gz u-boot-imx-bf4699db852f88b0a30b9d7e8b1bea83d01c0d92.tar.bz2 | |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040
T1040 SoC has SCFG (Supplement Configuration) Block which provides
chip specific configuration and status support. The base address of
SCFG block in T1040 is 0xfc000.
SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register)
at offset 0x28.
Add definition of
-SCFG block
-SCFG_PIXCLKCR register
-Bits definition of SCFG_PIXCLK register
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index edd7888..4b6f9d0 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1773,6 +1773,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 +#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 +#define PXCKEN_MASK 0x80000000 +#define PXCK_MASK 0x00FF0000 +#define PXCK_BITS_START 16 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 @@ -2863,6 +2867,7 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 +#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 @@ -2980,6 +2985,10 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) +#define CONFIG_SYS_FSL_SCFG_ADDR \ + (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) +#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ + (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) #define CONFIG_SYS_FSL_BMAN_ADDR \ |