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authorYork Sun <yorksun@freescale.com>2011-01-10 12:03:02 +0000
committerKumar Gala <galak@kernel.crashing.org>2011-01-19 22:58:24 -0600
commit6b06d7dc071a41e7c9d34447a18acdf53c6bdc4f (patch)
tree18e1a42ebf4eb5ee1e761c14e2911edc11a28788 /arch/powerpc/include
parentfa8d23c0ee5c66d5cda902ac6ea5b1dfc68d9712 (diff)
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corenet_ds: Extend board specific parameters
Extend board specific parameters to include cpo, write leveling override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_sdram.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index e6f0d32..852e5c3 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -120,6 +120,9 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define MD_CNTL_WRCW 0x00080000
#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN 0x80000000
+
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {