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authorYork Sun <yorksun@freescale.com>2012-05-07 07:26:47 +0000
committerAndy Fleming <afleming@freescale.com>2012-07-06 17:30:33 -0500
commit5e23ab0a31f19f894fe46bfab6f68b8bcfa10cf6 (patch)
tree48f508182cde09a202b6464599925a5415f2fed8 /arch/powerpc/include
parent48f6a5c348453fc3ab33aaa91e5e4198a28678ff (diff)
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powerpc/mpc85xx: Workaround for erratum CPU_A011
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f93ab62..b6c44bb 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -349,6 +349,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -373,6 +374,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -460,6 +462,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
#define CONFIG_SYS_P4080_ERRATUM_CPU22
+#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
#define CONFIG_SYS_P4080_ERRATUM_SERDES9
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001