summaryrefslogtreecommitdiff
path: root/arch/powerpc/include/asm
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2011-09-16 09:54:30 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-10-03 08:52:14 -0500
commit5ace2992b5a89afaa3144af4a076480651f4ddfa (patch)
tree33ea3a1a255e58c0440ee4efc6ade3a6e3adb693 /arch/powerpc/include/asm
parent568336ecc7083afd0b8b16a6b8b4a796491c142f (diff)
downloadu-boot-imx-5ace2992b5a89afaa3144af4a076480651f4ddfa.zip
u-boot-imx-5ace2992b5a89afaa3144af4a076480651f4ddfa.tar.gz
u-boot-imx-5ace2992b5a89afaa3144af4a076480651f4ddfa.tar.bz2
powerpc/mpc8548: Add workaround for erratum NMG_DDR120
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point. Signed-off-by: Gong Chen Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f9bf80d..a0a12b2 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -62,6 +62,7 @@
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1