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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2011-02-04 09:00:43 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-04 09:24:41 -0500 |
| commit | b6ccd2c9dee758a70e761403a41e60c31a1cfcec (patch) | |
| tree | c47fc0dc31ba8bf0f837eea05d0eebd48449cc4e /arch/powerpc/include/asm/ppc405ep.h | |
| parent | 24995d829aecc6abca0f1b41443ae0cd9b4fde5a (diff) | |
| download | u-boot-imx-b6ccd2c9dee758a70e761403a41e60c31a1cfcec.zip u-boot-imx-b6ccd2c9dee758a70e761403a41e60c31a1cfcec.tar.gz u-boot-imx-b6ccd2c9dee758a70e761403a41e60c31a1cfcec.tar.bz2 | |
fsl_pci: Add support for FSL PCIe controllers v2.x
FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.x
Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status register
Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.
To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/ppc405ep.h')
0 files changed, 0 insertions, 0 deletions