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authorYork Sun <yorksun@freescale.com>2013-09-16 12:49:31 -0700
committerYork Sun <yorksun@freescale.com>2013-10-16 16:15:17 -0700
commit133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a (patch)
tree8310923265a2fd56d900bc4b973cfbb2f95dfc75 /arch/powerpc/include/asm/immap_85xx.h
parente512c50bc9e3ef0bcf209620cabfc6ef35f22ff3 (diff)
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powerpc/mpc85xx: Add workaround for erratum A006379
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/immap_85xx.h')
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 00f17b6..e516e07 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1671,6 +1671,7 @@ typedef struct cpc_corenet {
#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000
#endif /* CONFIG_SYS_FSL_CPC */
/* Global Utilities Block */