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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2013-12-17 14:25:52 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-01-02 14:10:13 -0800 |
| commit | b135991a3cddd1a266c5fbd64e25eaaa61bde2d8 (patch) | |
| tree | 8969fd749e188219c441fa104bd6240e9f3e6b81 /arch/powerpc/include/asm/immap_85xx.h | |
| parent | 562de1d6da5bdc1789bd258d464d6ca57571861d (diff) | |
| download | u-boot-imx-b135991a3cddd1a266c5fbd64e25eaaa61bde2d8.zip u-boot-imx-b135991a3cddd1a266c5fbd64e25eaaa61bde2d8.tar.gz u-boot-imx-b135991a3cddd1a266c5fbd64e25eaaa61bde2d8.tar.bz2 | |
powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.
So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock
DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
normal clocking mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/immap_85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 672e8c6..68c3c82 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1774,6 +1774,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 |