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author | Dipen Dudhat <Dipen.Dudhat@freescale.com> | 2011-01-20 16:29:35 +0530 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-04 09:24:40 -0500 |
commit | d789b5f5bc18199fe617878efaa32756f481e7c8 (patch) | |
tree | 36ee9ef6d5bd64af6cdb373d221ef0bd85947e0f /arch/powerpc/include/asm/fsl_law.h | |
parent | 28747f9bb1623d8333c419ae679b914bcabd4836 (diff) | |
download | u-boot-imx-d789b5f5bc18199fe617878efaa32756f481e7c8.zip u-boot-imx-d789b5f5bc18199fe617878efaa32756f481e7c8.tar.gz u-boot-imx-d789b5f5bc18199fe617878efaa32756f481e7c8.tar.bz2 |
powerpc/85xx: Add support for Integrated Flash Controller (IFC)
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.
Features supported by IFC are,
- Functional muxing of pins between NAND, NOR and GPCM
- Support memory banks of size 64KByte to 4 GBytes
- Write protection capability (only for NAND and NOR)
- Provision of Software Reset
- Flexible Timing programmability for every chip select
- NAND Machine
- x8/ x16 NAND Flash Interface
- SLC and MLC NAND Flash devices support with
configurable
page sizes of upto 4KB
- Internal SRAM of 9KB which is directly mapped and
availble at
boot time for NAND Boot
- Configurable block size
- Boot chip select (CS0) available at system reset
- NOR Machine
- Data bus width of 8/16/32
- Compatible with asynchronous NOR Flash
- Directly memory mapped
- Supports address data multiplexed (ADM) NOR device
- Boot chip select (CS0) available at system reset
- GPCM Machine (NORMAL GPCM Mode)
- Support for x8/16/32 bit device
- Compatible with general purpose addressable device
e.g. SRAM, ROM
- External clock is supported with programmable division
ratio
- GPCM Machine (Generic ASIC Mode)
- Support for x8/16/32 bit device
- Address and Data are shared on I/O bus
- Following Address and Data sequences can be supported
on I/O bus
- 32 bit I/O: AD
- 16 bit I/O: AADD
- 8 bit I/O : AAAADDDD
- Configurable Even/Odd Parity on Address/Data bus
supported
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/fsl_law.h')
-rw-r--r-- | arch/powerpc/include/asm/fsl_law.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 6a4279c..ae45f9b 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -91,6 +91,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO +#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC #ifdef CONFIG_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI |