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author | York Sun <yorksun@freescale.com> | 2013-09-16 12:49:31 -0700 |
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committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:15:17 -0700 |
commit | 133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a (patch) | |
tree | 8310923265a2fd56d900bc4b973cfbb2f95dfc75 /arch/powerpc/include/asm/fsl_errata.h | |
parent | e512c50bc9e3ef0bcf209620cabfc6ef35f22ff3 (diff) | |
download | u-boot-imx-133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a.zip u-boot-imx-133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a.tar.gz u-boot-imx-133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a.tar.bz2 |
powerpc/mpc85xx: Add workaround for erratum A006379
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.
Erratum A006379 applies to
T4240 rev 1.0
B4860 rev 1.0, 2.0
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/fsl_errata.h')
-rw-r--r-- | arch/powerpc/include/asm/fsl_errata.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h new file mode 100644 index 0000000..3cac2d4 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -0,0 +1,25 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_FSL_ERRATA_H +#define _ASM_FSL_ERRATA_H + +#include <common.h> +#include <asm/processor.h> + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 +static inline bool has_erratum_a006379(void) +{ + u32 svr = get_svr(); + if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2)) + return true; + + return false; +} +#endif + +#endif |