Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/p3060: Add SoC related support for P3060 platform
  powerpc/85xx: Add support for setting up RAID engine liodns on P5020
  powerpc/85xx: Refactor some defines out of corenet_ds.h
  fm-eth: Add ability for board code to disable a port
  powerpc/mpc8548: Add workaround for erratum NMG_LBC103
  powerpc/mpc8548: Add workaround for erratum NMG_DDR120
  powerpc/mpc85xxcds: Fix PCI speed
  powerpc/mpc8548cds: Fix booting message
  powerpc/p4080: Add support for secure boot flow
  powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
  powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
  powerpc/p2041rdb: remove watch dog related codes
  powerpc/p2041rdb: updated description of cpld command
  powerpc/p2041rdb: add more ddr frequencies support
  powerpc/p2041rdb: set sysclk according to status of physical switch SW1
  powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
  powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc8xxx: Add DDR2 to unified DDR driver
  powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
  powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
  powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
  powerpc/85xx: Refactor P2041RDB to use common p_corenet files
  powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
  powerpc/85xx: Enable CMD_REGINFO on corenet boards
  powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
  powerpc/85xx: Fix USB protocol definitions for P1020RDB
  powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
  powerpc/mpc8xxx: Move DDR RCW overriding to common code
  powerpc/mpc8xxx: Extend CWL table
  powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
  powerpc/85xx: Cleanup extern in corenet_ds board code
  powerpc/p2041rdb: Add ethernet support on P2041RDB board
  powerpc/85xx: Add networking support to P1023RDS
  powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
  powerpc/85xx: Add FMan ethernet support to P4080DS
  powerpc/85xx: Add support for FMan ethernet in Independent mode
  powerpc/mpc8548cds: Cleanup mpc8548cds.c
  powerpc/mp: add support for discontiguous cores
  powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
  fdt: Add new fdt_create_phandle helper
  fdt: Rename fdt_create_phandle to fdt_set_phandle
  powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
  fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
  powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
  fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
  powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
  powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
  nand: Freescale Integrated Flash Controller NAND support
  powerpc/85xx: Add basic support for P1010RDB
  powerpc/85xx: Add support for new P102x/P2020 RDB style boards
  powerpc/85xx: relocate CCSR before creating the initial RAM area
  powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
  powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
  powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014

1 files changed, 69 insertions, 0 deletions

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 04ca989..c3d6ba9 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -23,6 +23,10 @@
 
 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
 
+#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
+#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
+#endif
+
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
 #define CONFIG_SYS_NUM_TLBCAMS		64
@@ -34,34 +38,43 @@
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8540)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8541)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8544)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8548)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8560)
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8568)
 #define CONFIG_MAX_CPUS			1
@@ -70,6 +83,7 @@
 #define QE_MURAM_SIZE			0x10000UL
 #define MAX_QE_RISC			2
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8569)
 #define CONFIG_MAX_CPUS			1
@@ -78,11 +92,13 @@
 #define QE_MURAM_SIZE			0x20000UL
 #define MAX_QE_RISC			4
 #define QE_NUM_OF_SNUM			46
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_MPC8572)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 
@@ -97,6 +113,10 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -105,6 +125,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -115,6 +136,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
@@ -127,6 +149,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
@@ -141,6 +164,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 
 /* P1015 is single core version of P1024 */
 #elif defined(CONFIG_P1015)
@@ -149,6 +176,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -164,6 +192,7 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 /* P1017 is single core version of P1023 */
 #elif defined(CONFIG_P1017)
@@ -177,6 +206,7 @@
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
 
 #elif defined(CONFIG_P1020)
 #define CONFIG_MAX_CPUS			2
@@ -184,6 +214,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -193,6 +224,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
@@ -204,6 +236,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
@@ -219,6 +252,7 @@
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
 
 /* P1024 is lower end variant of P1020 */
 #elif defined(CONFIG_P1024)
@@ -227,6 +261,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -237,6 +272,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
@@ -248,6 +284,7 @@
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 
@@ -255,6 +292,7 @@
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 
@@ -269,8 +307,10 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_PPC_P2041)
@@ -285,8 +325,10 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_PPC_P3041)
@@ -301,10 +343,27 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+#elif defined(CONFIG_PPC_P3060)
+#define CONFIG_MAX_CPUS			8
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_SYS_NUM_FM2_DTSEC	4
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+
 #elif defined(CONFIG_PPC_P4040)
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
@@ -313,6 +372,7 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS			8
@@ -328,6 +388,7 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@@ -354,8 +415,10 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #elif defined(CONFIG_PPC_P5020)
@@ -370,12 +433,18 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #else
 #error Processor type not defined for this platform
 #endif
 
+#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
+#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
+#endif
+
 #endif /* _ASM_MPC85xx_CONFIG_H_ */