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| author | Kumar Gala <galak@kernel.crashing.org> | 2011-01-13 01:56:18 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 01:32:22 -0600 |
| commit | 868da5936e40b8685c813c1eb31eed629eaae295 (patch) | |
| tree | fb0117876a75d0fa775e129d66366f20bf6a5915 /arch/powerpc/cpu | |
| parent | 1d2c2a62e328db22c38e3dfb3c0a8a373333471b (diff) | |
| download | u-boot-imx-868da5936e40b8685c813c1eb31eed629eaae295.zip u-boot-imx-868da5936e40b8685c813c1eb31eed629eaae295.tar.gz u-boot-imx-868da5936e40b8685c813c1eb31eed629eaae295.tar.bz2 | |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)
CoreNet Platform Cache single-bit data error scrubbing will cause data
corruption. Disable the feature to workaround the issue.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ae6af4f..bf70d2d 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -62,6 +62,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 puts("Work-around for Erratum CPC-A002 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 + puts("Work-around for Erratum CPC-A003 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index c822d87..8ece970 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -145,6 +145,9 @@ static void enable_cpc(void) #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 + setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); +#endif out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ |