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| author | Lan Chunhe <b25806@freescale.com> | 2010-04-21 07:40:50 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-04-26 22:37:56 -0500 |
| commit | 3f0202ed13add5fd6e2ed66fcb3f5e1228cdf766 (patch) | |
| tree | 3dac9f1dbe0ef81df743fd86289e46a6e7ba0cd4 /arch/powerpc/cpu | |
| parent | 0c955dafab495fef5a76f5383387281d0408056c (diff) | |
| download | u-boot-imx-3f0202ed13add5fd6e2ed66fcb3f5e1228cdf766.zip u-boot-imx-3f0202ed13add5fd6e2ed66fcb3f5e1228cdf766.tar.gz u-boot-imx-3f0202ed13add5fd6e2ed66fcb3f5e1228cdf766.tar.bz2 | |
mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b517e06..e578b29 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -260,6 +260,10 @@ void cpu_init_f (void) int cpu_init_r(void) { +#ifdef CONFIG_SYS_LBC_LCRR + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); +#endif + puts ("L2: "); #if defined(CONFIG_L2_CACHE) @@ -383,6 +387,17 @@ int cpu_init_r(void) #if defined(CONFIG_MP) setup_mp(); #endif + +#ifdef CONFIG_SYS_LBC_LCRR + /* + * Modify the CLKDIV field of LCRR register to improve the writing + * speed for NOR flash. + */ + clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); + __raw_readl(&lbc->lcrr); + isync(); +#endif + return 0; } |