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| author | Kumar Gala <galak@kernel.crashing.org> | 2011-02-18 05:40:54 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-28 22:09:24 -0500 |
| commit | 66412c6371cfd6e056679abedea7d6fafe6a0422 (patch) | |
| tree | 261d51ec7e7c2a22f0bd5db5fca43d4fc9910aeb /arch/powerpc/cpu | |
| parent | d90fdba6ca0b08c77cced6e914609e3696dd5909 (diff) | |
| download | u-boot-imx-66412c6371cfd6e056679abedea7d6fafe6a0422.zip u-boot-imx-66412c6371cfd6e056679abedea7d6fafe6a0422.tar.gz u-boot-imx-66412c6371cfd6e056679abedea7d6fafe6a0422.tar.bz2 | |
powerpc/85xx: Change timebase divisor to be defined per processor
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts. All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f5b39c0..f863f4a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -234,13 +234,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * Get timebase clock frequency */ +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif unsigned long get_tbclk (void) { -#ifdef CONFIG_FSL_CORENET - return (gd->bus_clk + 8) / 16; -#else - return (gd->bus_clk + 4UL)/8UL; -#endif + unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; + + return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; } |