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| author | Mark Marshall <Mark.Marshall@omicron.at> | 2017-01-24 15:40:23 +0100 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-01-31 17:51:34 -0800 |
| commit | 2ec70961e7dc6548451822857aca5dc2573cee55 (patch) | |
| tree | ea8b9954ec76b5de31687dc1b66a59740316a272 /arch/powerpc/cpu | |
| parent | dbcb2c0e2ba28fc61ab03f57de14f1085e69834f (diff) | |
| download | u-boot-imx-2ec70961e7dc6548451822857aca5dc2573cee55.zip u-boot-imx-2ec70961e7dc6548451822857aca5dc2573cee55.tar.gz u-boot-imx-2ec70961e7dc6548451822857aca5dc2573cee55.tar.bz2 | |
powerpc: mpc85xx: Use symbolic names for cache control bits
We should use the symbolic names for the cache control bits.
Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 932216c..eb817f1 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1373,8 +1373,8 @@ icache_enable: mtlr r8 isync mfspr r4,L1CSR1 - ori r4,r4,0x0001 - oris r4,r4,0x0001 + ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l + oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h mtspr L1CSR1,r4 isync blr @@ -1402,8 +1402,8 @@ dcache_enable: mtlr r8 isync mfspr r0,L1CSR0 - ori r0,r0,0x0001 - oris r0,r0,0x0001 + ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l + oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h msync isync mtspr L1CSR0,r0 |