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| author | Timur Tabi <timur@freescale.com> | 2012-03-26 09:49:08 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-04-24 23:58:34 -0500 |
| commit | 822ad60f1c37a79659dc5889eb2993a462c9a95f (patch) | |
| tree | 0bbaef47082487f00fe0bf913cfe247af985ced7 /arch/powerpc/cpu | |
| parent | 5d065c3e103133f811fdf77f6b793950fc3d3424 (diff) | |
| download | u-boot-imx-822ad60f1c37a79659dc5889eb2993a462c9a95f.zip u-boot-imx-822ad60f1c37a79659dc5889eb2993a462c9a95f.tar.gz u-boot-imx-822ad60f1c37a79659dc5889eb2993a462c9a95f.tar.bz2 | |
powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but
that register does not exist on e500v1.
Signed-off-by: Timur Tabi <timur@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 7bfa2d5..8e99ef6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -443,13 +443,15 @@ create_ccsr_new_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + mtspr MAS7, r7 +#endif mtspr MAS0, r0 mtspr MAS1, r1 mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe @@ -465,12 +467,14 @@ create_ccsr_old_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS li r7, 0 /* The default CCSR address is always a 32-bit number */ + mtspr MAS7, r7 +#endif mtspr MAS0, r0 /* MAS1 is the same as above */ mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe |