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| author | Timur Tabi <timur@freescale.com> | 2011-10-31 13:30:44 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-11-08 08:31:06 -0600 |
| commit | 19e438412416c4cd4066dfa7aca679fe291f13e1 (patch) | |
| tree | 3fdcdf65e520aeb01cc3f2e8a2b4b151896757c1 /arch/powerpc/cpu | |
| parent | 452ad61c3feeffbf2b5ff74f0a6797af3ba4882c (diff) | |
| download | u-boot-imx-19e438412416c4cd4066dfa7aca679fe291f13e1.zip u-boot-imx-19e438412416c4cd4066dfa7aca679fe291f13e1.tar.gz u-boot-imx-19e438412416c4cd4066dfa7aca679fe291f13e1.tar.bz2 | |
powerpc/85xx: verify the current address of CCSR before relocating it
Verify that CCSR is actually located where it is supposed to be before
we relocate it. This is useful in detecting U-Boot configurations that
are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT).
If the current value is wrong, we enter an infinite loop, which is handy
for debuggers.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index e519f35..d494528 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -411,6 +411,33 @@ create_ccsr_old_tlb: msync tlbwe + /* + * We have a TLB for what we think is the current (old) CCSR. Let's + * verify that, otherwise we won't be able to move it. + * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only + * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. + */ +verify_old_ccsr: + lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h + ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l +#ifdef CONFIG_FSL_CORENET + lwz r1, 4(r9) /* CCSRBARL */ +#else + lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ + slwi r1, r1, 12 +#endif + + cmpl 0, r0, r1 + + /* + * If the value we read from CCSRBARL is not what we expect, then + * enter an infinite loop. This will at least allow a debugger to + * halt execution and examine TLBs, etc. There's no point in going + * on. + */ +infinite_debug_loop: + bne infinite_debug_loop + #ifdef CONFIG_FSL_CORENET #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) |