Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	arch/arm/include/asm/mach-types.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

13 files changed, 117 insertions, 209 deletions

diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index 9cfdb0f..28926e0 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -37,11 +37,11 @@ COBJS-y += interrupts.o
 COBJS-y += iopin.o
 COBJS-y += serial.o
 COBJS-y += speed.o
-COBJS-${CONFIG_FSL_DIU_FB} += diu.o
-COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_diu_fb.o
-COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_logo_bmp.o
-COBJS-${CONFIG_CMD_IDE} += ide.o
-COBJS-${CONFIG_IIM} += iim.o
+COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
+COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o
+COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_logo_bmp.o
+COBJS-$(CONFIG_CMD_IDE) += ide.o
+COBJS-$(CONFIG_IIM) += iim.o
 COBJS-$(CONFIG_PCI) += pci.o
 
 COBJS	:= $(COBJS-y)
diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c
index b20234d..44b8a7a 100644
--- a/arch/powerpc/cpu/mpc5xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc5xxx/cpu.c
@@ -154,26 +154,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 }
 #endif
 
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-
-void bootcount_store (ulong a)
-{
-	volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB);
-
-	*save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | a;
-}
-
-ulong bootcount_load (void)
-{
-	volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB);
-
-	if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
-		return 0;
-	else
-		return (*save_addr & 0x0000ffff);
-}
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
-
 #ifdef CONFIG_MPC5xxx_FEC
 /* Default initializations for FEC controllers.  To override,
  * create a board-specific function called:
diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c
index 992e0ff..5df9735 100644
--- a/arch/powerpc/cpu/mpc8220/fec.c
+++ b/arch/powerpc/cpu/mpc8220/fec.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003
+ * (C) Copyright 2003-2010
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * This file is based on mpc4200fec.c,
@@ -27,10 +27,6 @@ static void tfifo_print (char *devname, mpc8220_fec_priv * fec);
 static void rfifo_print (char *devname, mpc8220_fec_priv * fec);
 #endif /* DEBUG */
 
-#ifdef DEBUG
-static u32 local_crc32 (char *string, unsigned int crc_value, int len);
-#endif
-
 typedef struct {
 	u8 data[1500];		/* actual data */
 	int length;		/* actual length */
@@ -962,39 +958,4 @@ int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
 	return 0;
 }
 
-#ifdef DEBUG
-static u32 local_crc32 (char *string, unsigned int crc_value, int len)
-{
-	int i;
-	char c;
-	unsigned int crc, count;
-
-	/*
-	 * crc32 algorithm
-	 */
-	/*
-	 * crc = 0xffffffff; * The initialized value should be 0xffffffff
-	 */
-	crc = crc_value;
-
-	for (i = len; --i >= 0;) {
-		c = *string++;
-		for (count = 0; count < 8; count++) {
-			if ((c & 0x01) ^ (crc & 0x01)) {
-				crc >>= 1;
-				crc = crc ^ 0xedb88320;
-			} else {
-				crc >>= 1;
-			}
-			c >>= 1;
-		}
-	}
-
-	/*
-	 * In big endian system, do byte swaping for crc value
-	 */
-	return crc;
-}
-#endif /* DEBUG */
-
 #endif /* CONFIG_MPC8220_FEC */
diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c
index 111a67c..c522bc5 100644
--- a/arch/powerpc/cpu/mpc8260/commproc.c
+++ b/arch/powerpc/cpu/mpc8260/commproc.c
@@ -195,27 +195,3 @@ ulong post_word_load (void)
 }
 
 #endif	/* CONFIG_POST || CONFIG_LOGBUFFER*/
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-
-void bootcount_store (ulong a)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR);
-
-	save_addr[0] = a;
-	save_addr[1] = BOOTCOUNT_MAGIC;
-}
-
-ulong bootcount_load (void)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR);
-
-	if (save_addr[1] != BOOTCOUNT_MAGIC)
-		return 0;
-	else
-		return save_addr[0];
-}
-
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 8b98a57..d3be909 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -304,33 +304,3 @@ int cpu_mmc_init(bd_t *bis)
 	return 0;
 #endif
 }
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-
-#if !defined(CONFIG_MPC8360)
-#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented"
-#endif
-
-#if !defined(CONFIG_BOOTCOUNT_ADDR)
-#define CONFIG_BOOTCOUNT_ADDR	(0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long))
-#endif
-
-#include <asm/io.h>
-
-void bootcount_store (ulong a)
-{
-	void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
-	out_be32 (reg, a);
-	out_be32 (reg + 4, BOOTCOUNT_MAGIC);
-}
-
-ulong bootcount_load (void)
-{
-	void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
-
-	if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC)
-		return 0;
-	else
-		return in_be32 (reg);
-}
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 75b4522..f3b67ae 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -65,16 +65,16 @@ void cpu_init_f (volatile immap_t * im)
 {
 	__be32 acr_mask =
 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
-		(ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
+		ACR_PIPE_DEP |
 #endif
 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
-		(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+		ACR_RPTCNT |
 #endif
 #ifdef CONFIG_SYS_ACR_APARK	/* Arbiter address parking mode */
-		(ACR_APARK << ACR_APARK_SHIFT) |
+		ACR_APARK |
 #endif
 #ifdef CONFIG_SYS_ACR_PARKM	/* Arbiter parking master */
-		(ACR_PARKM << ACR_PARKM_SHIFT) |
+		ACR_PARKM |
 #endif
 		0;
 	__be32 acr_val =
@@ -93,16 +93,16 @@ void cpu_init_f (volatile immap_t * im)
 		0;
 	__be32 spcr_mask =
 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
-		(SPCR_OPT << SPCR_OPT_SHIFT) |
+		SPCR_OPT |
 #endif
 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
-		(SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
+		SPCR_TSECEP |
 #endif
 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
-		(SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
+		SPCR_TSEC1EP |
 #endif
 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
-		(SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
+		SPCR_TSEC2EP |
 #endif
 		0;
 	__be32 spcr_val =
@@ -121,34 +121,34 @@ void cpu_init_f (volatile immap_t * im)
 		0;
 	__be32 sccr_mask =
 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
-		(SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
+		SCCR_ENCCM |
 #endif
 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
-		(SCCR_PCICM << SCCR_PCICM_SHIFT) |
+		SCCR_PCICM |
 #endif
 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
-		(SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
+		SCCR_TSECCM |
 #endif
 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
-		(SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+		SCCR_TSEC1CM |
 #endif
 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
-		(SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+		SCCR_TSEC2CM |
 #endif
 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
-		(SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
+		SCCR_TSEC1ON |
 #endif
 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
-		(SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
+		SCCR_TSEC2ON |
 #endif
 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
-		(SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
+		SCCR_USBMPHCM |
 #endif
 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
-		(SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+		SCCR_USBDRCM |
 #endif
 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
-		(SCCR_SATACM << SCCR_SATACM_SHIFT) |
+		SCCR_SATACM |
 #endif
 		0;
 	__be32 sccr_val =
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index a7c8079..c7d85a8 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -507,7 +507,7 @@ init_e300_core: /* time t 10 */
 
 	lis	r3, CONFIG_SYS_IMMR@h
 #if defined(CONFIG_WATCHDOG)
-	/* Initialise the Wathcdog values and reset it (if req) */
+	/* Initialise the Watchdog values and reset it (if req) */
 	/*------------------------------------------------------*/
 	lis r4, CONFIG_SYS_WATCHDOG_VALUE
 	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
@@ -520,7 +520,7 @@ init_e300_core: /* time t 10 */
 	li	r4, -0x55C7
 	sth	r4, SWSRR@l(r3)
 #else
-	/* Disable Wathcdog  */
+	/* Disable Watchdog  */
 	/*-------------------*/
 	lwz r4, SWCRR(r3)
 	/* Check to see if its enabled for disabling
@@ -739,6 +739,7 @@ setup_bats:
  * Note: requires that all cache bits in
  * HID0 are in the low half word.
  */
+#ifndef CONFIG_NAND_SPL
 	.globl	icache_enable
 icache_enable:
 	mfspr	r3, HID0
@@ -767,6 +768,7 @@ icache_status:
 	mfspr	r3, HID0
 	rlwinm	r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
 	blr
+#endif	/* !CONFIG_NAND_SPL */
 
 	.globl	dcache_enable
 dcache_enable:
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e578b29..99431dc 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Modified by Xianghua Xiao, X.Xiao@motorola.com
@@ -30,9 +30,11 @@
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <ioports.h>
+#include <sata.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -418,3 +420,13 @@ void arch_preboot_os(void)
 
 	setup_ivors();
 }
+
+#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
+int sata_initialize(void)
+{
+	if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
+		return __sata_initialize();
+
+	return 1;
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index cb6a6f0..7e72f5f 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -1,17 +1,31 @@
 /*
- * Copyright (C) 2008 Freescale Semicondutor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
  *	Dave Liu <daveliu@freescale.com>
  *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
  */
 
 #include <config.h>
 #include <common.h>
 #include <asm/io.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
 
 /* PORDEVSR register */
 #define GUTS_PORDEVSR_OFFS		0xc
@@ -52,6 +66,61 @@
 #define FSL_SRDSCR3_LANEE_SGMII	0x00000000
 #define FSL_SRDSCR3_LANEE_SATA	0x00150005
 
+
+#define SRDS1_MAX_LANES		8
+#define SRDS2_MAX_LANES		2
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+	[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
+	[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
+	[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
+	[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
+};
+
+static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
+	[0x1] = {SATA1, SATA2},
+	[0x3] = {SATA1, NONE},
+	[0x4] = {SGMII_TSEC1, SGMII_TSEC3},
+	[0x6] = {SGMII_TSEC1, NONE},
+};
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+	int i;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+
+	u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >>
+				GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
+
+	debug("%s: dev = %d\n", __FUNCTION__, device);
+	debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
+	debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg);
+
+	if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+		printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
+		return 0;
+	}
+
+	if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+		printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg);
+		return 0;
+	}
+
+	for (i = 0; i < SRDS1_MAX_LANES; i++) {
+		if (serdes1_cfg_tbl[srds1_cfg][i] == device)
+			return 1;
+	}
+	for (i = 0; i < SRDS2_MAX_LANES; i++) {
+		if (serdes2_cfg_tbl[srds2_cfg][i] == device)
+			return 1;
+	}
+
+	return 0;
+}
+
 void fsl_serdes_init(void)
 {
 	void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/arch/powerpc/cpu/mpc8xx/commproc.c b/arch/powerpc/cpu/mpc8xx/commproc.c
index a87a0dc..2c85377 100644
--- a/arch/powerpc/cpu/mpc8xx/commproc.c
+++ b/arch/powerpc/cpu/mpc8xx/commproc.c
@@ -103,29 +103,3 @@ ulong post_word_load (void)
 }
 
 #endif	/* CONFIG_POST || CONFIG_LOGBUFFER*/
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-
-void bootcount_store (ulong a)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem +
-		                    CPM_BOOTCOUNT_ADDR );
-
-	save_addr[0] = a;
-	save_addr[1] = BOOTCOUNT_MAGIC;
-}
-
-ulong bootcount_load (void)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem +
-		                    CPM_BOOTCOUNT_ADDR );
-
-	if (save_addr[1] != BOOTCOUNT_MAGIC)
-		return 0;
-	else
-		return save_addr[0];
-}
-
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
index d9d0fa7..dcb37ce 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
@@ -175,8 +175,8 @@ determine_refresh_rate_ps(const unsigned int spd_refresh)
  * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
  * Not certain if any good value exists for CL=2
  */
-				 /* CL2   CL3   CL4   CL5   CL6 */
-unsigned short ddr2_speed_bins[] = {   0, 5000, 3750, 3000, 2500 };
+				 /* CL2   CL3   CL4   CL5   CL6  CL7*/
+unsigned short ddr2_speed_bins[] = {   0, 5000, 3750, 3000, 2500, 1875 };
 
 unsigned int
 compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
index 85995ca..186936f 100644
--- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
+++ b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
@@ -56,18 +56,6 @@ static struct pci_info pci_config_info[] =
 #elif defined(CONFIG_MPC8536)
 static struct pci_info pci_config_info[] =
 {
-	[LAW_TRGT_IF_PCI] = {
-		.cfg =   0,
-	},
-	[LAW_TRGT_IF_PCIE_1] = {
-		.cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
-	},
-	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 5) | (1 << 7),
-	},
-	[LAW_TRGT_IF_PCIE_3] = {
-		.cfg =   (1 << 7),
-	},
 };
 #elif defined(CONFIG_MPC8544)
 static struct pci_info pci_config_info[] =
diff --git a/arch/powerpc/cpu/ppc4xx/commproc.c b/arch/powerpc/cpu/ppc4xx/commproc.c
index a1696d3..6bf95e6 100644
--- a/arch/powerpc/cpu/ppc4xx/commproc.c
+++ b/arch/powerpc/cpu/ppc4xx/commproc.c
@@ -51,27 +51,3 @@ ulong post_word_load (void)
 }
 
 #endif	/* CONFIG_POST || CONFIG_LOGBUFFER*/
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-
-void bootcount_store (ulong a)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
-
-	save_addr[0] = a;
-	save_addr[1] = BOOTCOUNT_MAGIC;
-}
-
-ulong bootcount_load (void)
-{
-	volatile ulong *save_addr =
-		(volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
-
-	if (save_addr[1] != BOOTCOUNT_MAGIC)
-		return 0;
-	else
-		return save_addr[0];
-}
-
-#endif /* CONFIG_BOOTCOUNT_LIMIT */